Here's hoping there are some people here who can assist with my question.
I am planning to us a couple of AD7685 in a daisy chain configuration (not using busy/ack).
I will be running this using a (microcontroller) timer to generate the CNV signal and a trigger 3.2us later to start the SPI Transfer (using DMA). The idea is that the timer will repeat the process for a number of samples/cycles - but I will be using the DMA RX Tfr counter to signal when I have received the data from the final transfer. The timer will then be stopped.
However, it is highly unlikely that I will get to stop the timer before the next CNV signal is asserted. The question I have is does it matter if the CNV signal is set low before either the conversion of the acqusition phase is complete? If this is OK will I have to wait a minimum time before starting a brand new conversion/acqusition cycle?
Hope this makes sense