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AD7766-2 Flatline

We are using two AD7766-2 ADCs in our application, read by an FPGA.  We've seen very occasionally (<1%) where one channel will not initialize properly and never trigger DRDY.  Toggling the SYNC/PD lines does not solve the problem.  Has anyone seen this before, or are there any power-on sequencing requirements that I need to be aware of?

Thanks,

Brian

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