om my board There is one ad7799 and ad420 .
after setup ad7799 I realized that unlike ad7799 the ad420 need clock
to be low in ideal state .
is there any solution for this problem ?
and as i see in ad420 it accept all data in Data in and just after rise edge apply data .
is there probably any problem that on same spi there is another communication .
is it guarantee that just the last word before latch is applied ?
My understanding is that you are asking if there will be no problems if two devices using SPI protocol will be using the same CLK and DATA lines. As long as they have different chip select pins (/CS for AD7799 and LATCH for AD420) you should have no problem with the SPI protocol.
You may want to take a look at this App Note (AN-1248) regarding the SPI protocol.