My interest is in the AD7175-2 specifically, but the question applies to all delta-sigma ADCs. The data sheets don't specify the data rate used for the INL specifications; would it be the lowest (5 SPS)?
How does the AD7175-2's INL vary with data rate? Does the INL deteriorate, or improve (unlikely I guess) at higher speeds? Do all sigma-delta ADCs behave similarly in this regard or does the order/architecture have a big impact?
I had assumed that the data rate of delta-sigma ADCs is determined by the amount of oversampling and all done in the digital domain in the filtering/decimation rather than by varying the modulator rates. I also presumed that INL errors arise in the analogue stages and thus would be independent of the data rate, but now I'm not sure.
I ask because I want to do low speed, high resolution measurements but would prefer to sample at a higher rate of 1kSPS, or even 10k, and filter/average externally so that I also get the higher speed (but noisier) samples at the same time. Would the higher sampling rate negatively impact the INL and if so would the external filtering improve it?
If the filtering does impact the INL, what would be the best type of filter to use to minimize linearity errors?
Thank you for your comprehensive answer - just what I need to know. To be honest it was what I expected except for recently having looked at the LTC2400 and LTC2440 datasheets which show that their INL does vary with data-rate. That is presumably due to their 'unique' architecture, but to be fair the AD7175-2 documentation doesn't detail its internal architecture so I don't think it was an unreasonable question.
Can you suggest any suitable buffer amplifier(s) to convert from single-ended to differential conversion that can match (or at least get close to) the internal buffer’s noise performance and won’t degrade its linearity for frequencies below, say, 10Hz? Should I be asking on the amplifier forum instead?