configuring AD7682

Background/Use case:

4 analog sensors

  • - AC output range of ~+/- 0.5Vpk-pk
  • - DC offset of 1.65V
  • - Output impedance ~ 32kΩ +/- 8kΩ
  • - Output drives ADA4841-x buffers, which drive ADC inputs CH1-4
  • - sampled at 800 Sa/s
  • - 4 Sensor star grounds short to system ground (GND) at ADC COM pin
  • - 4 Sensors must be sampled with synchronous clocks

AD7682 set up

  • - Digital rail is derived from system 3.3V LDO into VDD and VIO pins
  • - External reference at 3.3V, derived from system 3.3V LDO digital rail, pi filtered, internally buffered, 10uF cap on REF pin, 100nF cap on REFIN pin
  • - CFG register,
    • INCC = Unipolar or Bipolar (TBD) referenced to COM
    • Inx = 11b (CH3)
    • BW = 0 (1/4 BW)
    • REF = 111b (Ext ref, internal buffer, temp disabled)
    • SEQ = 11b (Sequencer enabled, scan IN0 to IN3)
    • RB = 0 (do not read back)
  • - SPI timing in RAC mode, sequencer enabled, with busy indicator
  • - CH 1-4 sampled in continuous mode

 

  1. Based on this excerpt from the data sheet for the AD7682: “digital activity occurs only prior to the safe data reading/writing time, tDATA, because the AD7682/AD7689 provide error correction circuitry that can correct for an incorrect bit during this time. From tDATA to tCONV, there is no error correction, and conversion results may be corrupted. Configure the AD7682/AD7689 and initiate the busy indicator (if desired) prior to tDATA.” … This indicates to operate the ADC in RAC mode for best performance, correct?
  2. Do not fully understand the busy indicator … comparing timing diagram in Figure 40 to Figure 39 for RAC, it appears the SDO goes low to indicate host should write conf reg and read data, and the quiet time is over
  3. Does the host need to continuously write the CFG register… I would assume not if it does not need to change
  4. Is it correct that the conversion time is fixed?
  5. How can I control the conversion time?
  6. If possible to slow conversion time, will this minimize noise by running as slow as possible?
  7. Using the EVAL-AD76MUXEDZ and EVAL-CED1Z, is it possible to capture continuous data and save it to file for post processing and analysis?
  8. Referring to Figure 40… to run in RAC mode, 4 CH sequencer enabled, with busy indicator… I made this list of SPI events psuedocode, please review
  9. HOST POR

 

  1. HOST SS to AD7682 CNV: 0 -> 1 SOC (start Tconv(n-2)), hold for min 10ns
  2. HOST SS to AD7682 CNV: 1 -> 0 (must before AD7682 asserts busy indicator)
  3. AD7682 SDO: HIZ -> 0 (busy indicator) EOC
  4. HOST SCK to AD7682 SCK: 17 CLKs
    1. HOST MOSI to AD7682 DIN (CFG(n)) (sequencer enabled)
    2. AD7682 SDO to HOST MISO (DATA(x))

 

  1. HOST SS to AD7682 CNV: 0 -> 1 SOC (start Tconv(n-1)), hold for min 10ns
  2. HOST SS to AD7682 CNV: 1 -> 0 (must before AD7682 asserts busy indicator)
  3. AD7682 SDO: HIZ -> 0 (busy indicator) EOC
  4. HOST SCK to AD7682 SCK: 17 CLKs
    1. HOST MOSI to AD7682 DIN (CFG(n+1)) (sequencer enabled)
    2. AD7682 SDO to HOST MISO (DATA(x))

 

  1. HOST SS to AD7682 CNV: 0 -> 1 SOC (start Tconv CH0(n)), hold for min 10ns
  2. HOST SS to AD7682 CNV: 1 -> 0 (must before AD7682 asserts busy indicator)
  3. AD7682 SDO: HIZ -> 0 (busy indicator) EOC
  4. HOST SCK to AD7682 SCK: 17 CLKs
    1. HOST MOSI to AD7682 DIN (CFG(n+2)) (sequencer enabled)
    2. AD7682 SDO to HOST MISO (DATA CH0 (n))

 

  1. HOST SS to AD7682 CNV: 0 -> 1 SOC (start Tconv CH1(n+1)), hold for min 10ns
  2. HOST SS to AD7682 CNV: 1 -> 0 (must before AD7682 asserts busy indicator)
  3. AD7682 SDO: HIZ -> 0 (busy indicator) EOC
  4. HOST SCK to AD7682 SCK: 17 CLKs
    1. HOST MOSI to AD7682 DIN (CFG(n+3)) (sequencer enabled)
    2. AD7682 SDO to HOST MISO (DATA CH1 (n+1))

 

  1. HOST SS to AD7682 CNV: 0 -> 1 SOC (start Tconv CH2(n+2)), hold for min 10ns
  2. HOST SS to AD7682 CNV: 1 -> 0 (must before AD7682 asserts busy indicator)
  3. AD7682 SDO: HIZ -> 0 (busy indicator) EOC
  4. HOST SCK to AD7682 SCK: 17 CLKs
    1. HOST MOSI to AD7682 DIN (CFG(n+4)) (sequencer enabled)
    2. AD7682 SDO to HOST MISO (DATA CH2 (n+2))

 

  1. HOST SS to AD7682 CNV: 0 -> 1 SOC (start Tconv CH3(n+3)), hold for min 10ns
  2. HOST SS to AD7682 CNV: 1 -> 0 (must before AD7682 asserts busy indicator)
  3. AD7682 SDO: HIZ -> 0 (busy indicator) EOC
  4. HOST SCK to AD7682 SCK: 17 CLKs
    1. HOST MOSI to AD7682 DIN (CFG(n+5)) (sequencer enabled)
    2. AD7682 SDO to HOST MISO (DATA CH3 (n+3))

 

  1. HOST SS to AD7682 CNV: 0 -> 1 SOC (start Tconv CH0(n+4)), hold for min 10ns
  2. HOST SS to AD7682 CNV: 1 -> 0 (must before AD7682 asserts busy indicator)
  3. AD7682 SDO: HIZ -> 0 (busy indicator) EOC
  4. HOST SCK to AD7682 SCK: 17 CLKs
    1. HOST MOSI to AD7682 DIN (CFG(n+6)) (sequencer enabled)
    2. AD7682 SDO to HOST MISO (DATA CH0 (n+4))

ETC...

  • 0
    •  Analog Employees 
    on Jul 24, 2015 12:43 AM

    Hi,

    I am checking on this. I'll get back to you with a response soon.

    Regards,

    Karen

  • 0
    •  Analog Employees 
    on Jul 26, 2015 5:02 PM

    Hi,

    Your connections and configuration settings look correct.

    1. Performance can be achieved with either modes but the advantage of RAC would be that you would not need a fast clock, as the only time restriction is that the reading/writing must take place during the minimum acquisition time. This is further clarified in the timing diagram on this thread.

    2. The  gating item for both CFG and data readback is at the end of conversion (EOC). At EOC, if CNV is high, the busy indicator is disabled; if CNV is low, the busy indicator is enabled and SDO is returned to low. In addition, to generate the busy indicator properly, the host must assert a minimum of 17 SCK falling edges to return SDO to high impedance because the last bit on SDO remains active as shown in figure 38. If the CFG readback is enabled, a total of 31 SCK falling edges is required to return SDO to high-Z.

    3. Note that there is always a one deep delay when writing the CFG register. At power-up, the CFG register is undefined and two dummy conversions are required to update the register. CFG[13] would dictate whether to keep or overwrite the register contents. Keep in mind that the CFG word is updated on the first 14 SCK rising edges.

    4. Conversion time is not fixed  and you can vary it up to maximum 3.2 µs as specified in the table 5. Basically, the conversion time and acquisition time makes up the throughput (1/tcyc) of the SAR ADC and since you are running the ADC only at 800 SPS, your acquisition time can be further relaxed to run the part at lower throughput.

    5. See #4 above.

    6. There shouldn’t be any impact on noise performance if you run the ADC at slower throughput and you should meet the noise specs specified in the datasheet for a given reference voltage.

    7. There is a save button in the lower right portion of the software where you can save an html report of the current tab, a spreadsheet of data arrays of the various tabs, or a config file that can be reloaded at a later time. Our evaluation softwares do not support continuous saving of raw data so you will need to write your own software drivers to do this.

    8. This should be fine since you are not enabling CFG readback and following the datasheet recommendation to “keep the digital pins quiet for approximately 20 ns before and 10 ns after the rising edge of CNV. Make sure you configure the host to update SDO signal on falling edge instead of rising edge.”

    Have a look at the FGPA reference design available on our website to see how we implement the SPI communication between the ADC and host.

    Regards,

    Karen

  • 0
    •  Analog Employees 
    on Aug 2, 2018 3:07 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin