I have question regarding AD7985 3-wire interface mode without busy indicator (Figure 27 in datasheet). In page 18 of the datasheet, the number of bits that can be read during conversion is calculated by multiplying tDATA with fSCK. Then Figure 27 shows tDATA period starting from rising edge of the start of conversion pulse. Since SCK is not clocked when CNV is high, shouldn't the number of bits that can be read during conversion be (tDATA - tCNVH) * fSCK? Or does the tDATA period start at the falling edge of CNV?