I have question regarding AD7985 3-wire interface mode without busy indicator (Figure 27 in datasheet). In page 18 of the datasheet, the number of bits that can be read during conversion is calculated by multiplying tDATA with fSCK. Then Figure 27 shows tDATA period starting from rising edge of the start of conversion pulse. Since SCK is not clocked when CNV is high, shouldn't the number of bits that can be read during conversion be (tDATA - tCNVH) * fSCK? Or does the tDATA period start at the falling edge of CNV?
On the AD7985, the MSB is output onto the SDO when the CNV goes low, then the remaining data bits are clocked out on the subsequent SCK falling edges. It would need 16 SCK falling edges to complete the data fromthe AD7985, there would be a time to read during conversion.
I think I will need to get back to you on your point from your above statement, which I think it make sense, with regards to when the Tdata should start when reading during conversion.
You are correct, I think you need to consider the Tcnv and the Tenable times in reading the during conversion. That would mean that reading during conversion time would be, Tdata - (Tcnvh +Tenable).
Thanks Jonathan for taking time to check it. I got a similar answer from a local Analog Devices application engineer. I hope Analog Devices will update the datasheet to correct SCK frequency calculations in page 18.