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AD7682 severely influences input signal


In a current design for a test system, we use a power supply circuit with variable current limit and voltage setting. This circuit is controlled with DAC's and measured with ADC's (AD7949BCPZ).

Attatched picture "PSU circuit.jpg" shows the circuit. In this circuit, the ports 'PSU_Imeas' and 'PSU_Vmeas' are connected to ADC inputs. This circuit operates exactly as intended.

When operating the ADC, it is impossible to achieve accurate readings. After investigation we notice a strange phenomenom: when the ADC acquires data, the signal it is supposed to measure is pulled to ground, followed by heavy oscillations.

The effect is more pronounced at PSU_Imeas, but nonetheless present at the PSU_Vmeas node.
Attached to this post you can find a screenshot of what we see on the oscilloscope, where the yellow signal is the ADC CONV signal and blue is the PSU_Imeas node.

We tried replacing the ADC with different models in the same family: the AD7682 and AD7689. Both gave similar results.

We checked the opamp datasheet, it should not have any problem driving the load.

Has anyone seen this happen in their project? Any idea what it might be caused by?
  • Hello Harry,

    Thank you for responding. You seem to have a lot more experience than me (and my colleagues).

    I will read through the two articles you referenced (and apparently authored), but before I do I'd like to respond to some of the things you mentioned.

    I admit I did not put very much thought in the selection of the opamp. I do not need the 100MHz bandwidth. What I was looking for was the high slew rate, allowing the circuit to react to fast dynamic loads, and rail-to-rail output. That being said, I do not see how the extra bandwidth would be a disadvantage, or how resistor values in the 10k range could negatively impact the circuit. Would you mind elaborating on this?

    I understand that these Op Amps can only drive a limited capacitive load, this was actually the first thing I checked. But considering the ADC has a built in series resistor of 2.2k (and selectable 19k), I did not think this would be a problem. Besides, the PSU_Vmeas node experiences the same phenomenon, despite the 10k resistor in series with the ADC.

    Removing the 1nF capacitor from the feedback of OP3D did not affect the results.

    I did not intend to use these Op Amps as comparators, as far as I'm aware of. parts A and B are basically amplifying the DAC voltages. Their feedback is provided by parts C and D. Part C is again a unity gain buffer of the voltage at 'PSU_OUT', with the resistor divider in place, part A will attempt to drive the transistor until 'PSU_OUT' has twice the voltage set by the DAC. Part C will then compare the voltages at either end of the 10 Ohm resistor, resulting in an output voltage proportional to the current in that resistor, which is then used as feedback to part B. The diode array then allows part A or B, whichever has the lower output voltage, to determine how much T1 is driven.

    Nowhere in this circuit there is any hard high or low as there would be expected from a comparator.

    Thank you, harry, for spending time on this. I appreciate it and consider this a huge learning opportunity.

  • Harry,

    I don't think T1 actually 'shuts off'. It will always be driven to supply current, but limited to the amount allowed. I would expect some overshoot after a sudden transition to over current, but not oscillation.

    As I mentioned, the circuit itself seems to work as intended. Until the ADC samples, that's when it gets upset.


  • Harry,

    I'll give you some numbers to go with the schematic:

    PSU_Filt: 8V

    PSU_Vset: 0-3.3V (translating into an output voltage of 0-6.6V, but we intend to stay below 4V)

    PSU_Iset: 0-3.3V (translating into a current compliance settable between 0 and 330mA)

    Excepted peak load current: ~75mA in the current design

    As for the ADC, there's not much to see but I added it in attachment to this post.


  • The reason why the ADC sampling is having such a big influence is because your phase margin is very marginal ;-)

    Remove the ADC connection and instead AC couple the output of a signal generator into the node where the ADC would normally attach. You can sweep the generator with a sine wave to get an idea of stability or just use a square wave as a catch all.

    You will see your output go nuts.


  • FormerMember
    0 FormerMember
on Oct 29, 2015 5:55 PM


I'm having trouble figuring out exactly what you want to do, but some comments:

--  Resistor values too high around a 100 MHz op amp.

--  RRO op amps have higher output impedance and can't drive much capacitance;  looks like

   the 6207 is good for about 20 pF.  SAR ADCs have dynamic input impedance.  This is probably

   what is going on.  Use an isolation resistor;  see op amp d.s.  Or add an R-C anti-aliasing filter

--  You are using 3mV op amps w/ a 16 bit converter?  For precision analog, I am not a fan of quads.  See:


Planet Analog - Articles - Op amps: to dual or not to dual? (Part 2 of 2)

--  Op amps, comparators, and InAmps are all drawn as triangles;  they are NOT the same.  I NEVER

   use an op amp as a comparator.  See footnote 2 in the reference above.

--  Try an ADA4084-4 or an ADA4096-4.


  • Bert,

      Whether you use an op amp or a real comparator, if the input signal goes slowly through the threshold,

    you can get oscillation, so hysteresis should always be used around a comparator function.  See fig 6 in:

    Even with hysteresis added, it seems to me when you get an over current condition, the comparator will

    shut off T1, but then you don't have an over current condition, so T1 will turn back on.  So you should

    get an "oscillation" from the topology itself without a latch function.


  • try adding 1nF capacitors between pin 1 and 3, 6 and 7 of LT6207

    see if you get any improvement

  • Bert,

      With 2 pF of input capacitance and 1pF of pc board stray, a 10k feedback resistor will give

    you a pole at 5.3 MHz where the op amp has lots of gain.  We have op amps with 5,000 V/us SR

    and gbw over 1 GHz, so we get a lot of calls and emails:  "Why is my op amp oscillating...."

    GBW is similar to hamburgers:  If you have 90% lean ground beef, it's dry, if you have 60% lean,

    it's a grease burger.  You need enough gbw to do the job, but not a lot more.

    BTW, what supply voltage(s) on the op amp??

    When loops are large, the time delay can affect the stability.  I like to have local feedback on each

    stage when cascading multiple stages.

    I don't think you really need OP3C.  You just add offset.  R43 should be able to drive R47 and R48 directly.

    If OP3D is meant to be the classic four resistor difference amp, then you need a matching cap across

    R49 equal to C150, otherwise, your AC CMRR is poor.

    Can you show a bit more of the schematic over to the ADC?


  • Bert,

    You had mentioned earlier:

    "...The effect is more pronounced at PSU_Imeas, but nonetheless present at the PSU_Vmeas node."

    You could try one or all of the following experiments:

    --  Switch to a slower op amp

    --  Cut the traces over to the ADC and insert 100 ohm resistors.

    --   Add a 22 pF cap to PSU1_Imeas and see if the problem gets worse

    --  Change all your 10k resistors to 2k.  Even if the oscillation doesn't go away, record the amplitude

      and frequency before and after.


  • Hi,

    Can you share the timing screenshots clearly showing CNV, DIN, SCK, and SDO together?  At the point where you see the heavy oscillations, did you monitor the signal at the ADC analog inputs?