AD7177-2 Sample Clock input - LVPECL levels OK?

Hello,

We are working on a 8 ADC system, based on the AD7177-2 ADC.

Can the AD7177-2 sample clock input be driven by LVPECL levels?

I would like to use the Hittite HMC987LP5E 1:9 Fanout Buffer as the clock distributor from a 16MHz clock generator.

Will this work?

Do the SPI clocks need to be synchronized with the sampling clock?

Thank you,

Dan

  • 0
    •  Analog Employees 
    on Nov 3, 2015 12:27 AM

    Hi, Dan.

    The AD7177-2 can be driven from an external clock as long as it still meets the datasheet specifications. However, in your case I think it is not advisable to use the Hittite HMC987LP5E since it has a maximum operating frequency of 8GHz and you only need 16MHz clock. Usually, clock distributors with LVPECL are used to drive High Speed ADCs while Precision ADCs mostly use the internal clock since it is already guaranteed for optimum performance.

    SPI clock is provided by your microcontroller. It is different with your sampling clock so they are not necessary to be synchronized. However, if you want to synchronized the sampling of your ADCs you can use the /SYNC pin.

    Thanks,

    Jellenie

  • Jellenie,

    Thank you for the reply.

    We cannot use the on-board 16MHz clocks, for two reasons:

    1. They are only specified to +/-2.5% accuracy.

    2. Given a only 10Hz mismatch between two of the clocks, (16000000MHz and 16000010MHz), there will be a 10Hz spur generated. Extend this logic to 8 independent sampling clocks with +/-2.5% accuracy, and the noise spurrs are unpredictable.

    We are interested in very accurate measurements 25+ ENOB in the <10Hz range, for all channels.

    All the ADC sampling clocks need to be synchronized.

    The potential noise spurs are also the reason I ask about synchronizing the SPI clock to the sampling clocks.

    Achieving 25 ENOB in 8 ADCs at once is a difficult task that needs to take this into account. Do you have any data or application notes you migth point me toward?

    Thank you,

    Dan

  • 0
    •  Analog Employees 
    on Nov 3, 2015 11:27 PM

    Hi, Dan.

    Apologies, but I think I need to know more about what you are trying to achieve. May I know what is your target application?

    ENOB are used to measure ADC's dynamic performance which means an AC (sine wave) input to the ADC. The AD7177-2 is designed for low bandwidth inputs (essentially DC) and noise performance is specified by effective resolution and noise free resolution which does not concern spectral distortion. The part is specified with 24.6 noise free bits and 26.7 effective resolution at 5 SPS output data rate using Sinc5+Sinc1 filter. Regarding the clock, multiple AD7177-2 can be synchronized from a common master clock using SYNC pin, It can be a crystal or external or the master clock from one part can be brought out and used as the master clock for all 8 devices. 

    Thanks,

    Jellenie

  • 0
    •  Analog Employees 
    on Aug 2, 2018 3:15 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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