Is I2C Clock required in AD7992 Automatic Cycle Conversion mode?

Hi All,

We are using AD7992 analog to digital converter in our new

 

DWDM-PON based ONT design. The preferred mode of operation for the

 

converter is Mode 3 i.e. the Automatic cycle mode. Please confirm

 

whether the I2C clock is used for polling or reading the status of the A/D converter by the Soc.

 

Regards,

Mayank Khandoori

  • 0
    •  Analog Employees 
    on Dec 1, 2015 3:34 PM

    Hi Mayank,

    The conversion clock used in Mode 3 (Automatic cycle mode) is provided by an on chip oscillator. The conversion clock period is specified in the “Cycle timer” register.  As the I2C bus should be quite during a conversion (in order to achieve performance) the AD7992 has a feature in which it can delay a conversion and/or delay a bit trial if there is any activity detected on the I2C bus. This feature can be enabled by configuring bits D7 and D8 in the “Cycle Timer” register.

    When in placed Mode 3 the AD7992 will continuously sample the input without any interaction needed from a Microcontroller/FPGA/SOC. Once an ALERT interrupt signal occurs, the out of limit data can be read back by
    addressing the AD7992 and reading back the last ADC result from the “Conversion Result Register” . This involves setting the AD7992 “address pointer” register to point to the “Conversion Result” Register (which only needs to be done once), and then performing a two byte read each time an ALERT interrupt occurs. See Fig. 29 in the AD7992 data sheet for a timing diagram describing how to perform a Two Byte Read.

    Regards,

    Bing

  • 0
    •  Analog Employees 
    on Aug 2, 2018 3:15 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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