Is I2C Clock required in AD7992 Automatic Cycle Conversion mode?

Hi All,

We are using AD7992 analog to digital converter in our new

 

DWDM-PON based ONT design. The preferred mode of operation for the

 

converter is Mode 3 i.e. the Automatic cycle mode. Please confirm

 

whether the I2C clock is used for polling or reading the status of the A/D converter by the Soc.

 

Regards,

Mayank Khandoori

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  • Hi Bing,

    In the datasheet it is given that :

    "It is recommended that no I2C bus activity occurs when a conversion is taking place.

    However, this may not be possible,for example, when operating in Mode 2 or the automatic cycle mode. In order to maintain the performance of the ADC in such cases, Bits D7 and D6 in the cycle timer register are used to delay critical sample intervals and bit trials from occurring while there is activity on the I2C bus. This may have the effect of increasing the conversion time."

    Does this mean that the clock used in the automatic cycle mode during the conversion is provided by the on-chip oscillator of the A/D converter or the I2C clock is used for conversion? Please clarify.

    In our design, the A/D converter samples data at time intervals fixed in the cycle timer register and does the conversion. In case the resultant data violates the limits set in limit register, the A/D converter sends the ALERT interrupt signal to the SoC which reads the out of limit data from the A/D converter through the I2C bus. How does the I2C clock of the SoC initiates to read the data? Does the A/D converter sends an initiation signal to the SoC to indicate start of data read or the SoC continously keeps on polling the data from the A/D converter? Kindly look into this and confirm how data transmission initiates through I2C?

    Regards,

    Mayank

Reply
  • Hi Bing,

    In the datasheet it is given that :

    "It is recommended that no I2C bus activity occurs when a conversion is taking place.

    However, this may not be possible,for example, when operating in Mode 2 or the automatic cycle mode. In order to maintain the performance of the ADC in such cases, Bits D7 and D6 in the cycle timer register are used to delay critical sample intervals and bit trials from occurring while there is activity on the I2C bus. This may have the effect of increasing the conversion time."

    Does this mean that the clock used in the automatic cycle mode during the conversion is provided by the on-chip oscillator of the A/D converter or the I2C clock is used for conversion? Please clarify.

    In our design, the A/D converter samples data at time intervals fixed in the cycle timer register and does the conversion. In case the resultant data violates the limits set in limit register, the A/D converter sends the ALERT interrupt signal to the SoC which reads the out of limit data from the A/D converter through the I2C bus. How does the I2C clock of the SoC initiates to read the data? Does the A/D converter sends an initiation signal to the SoC to indicate start of data read or the SoC continously keeps on polling the data from the A/D converter? Kindly look into this and confirm how data transmission initiates through I2C?

    Regards,

    Mayank

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