We are using AD7992 analog to digital converter in our new
DWDM-PON based ONT design. The preferred mode of operation for the
converter is Mode 3 i.e. the Automatic cycle mode. Please confirm
whether the I2C clock is used for polling or reading the status of the A/D converter by the Soc.
This is to acknowledge the receipt of your email. I'll look into this and update you as soon as possible.
Yes I2c clock or SCL is still required in Automatic mode. This is where your data is being clock out. The SDAline is where the communication between the master and slave and where the exchange of data takes place. It tells that the transmission lines area ready to start or acknowledges the data from SDA. For Soc (system onchip), it is also used in.
Thanks for reply.
We have used AD8304 logarithmic amplifier along with AD7992 A/D converter in our design. PFA the schematic for the design and provide a feedback on it. The photodiode has been provided both adaptive biasing through VPDB pin that provides 0.6V-2.6V ,as well as an external bias from a 5V source. The dark current for photodiode at 5V reverse bias is given as 2.5nA and the minimum required input current at AD8304 input is 0.1nA. Kindly, clarify if applying 5V reverse bias to the photodiode will interfere with normal functioning of AD8304.
In another configuration we have used AD8153 switch to multiplex signals from two SFFs on a single lane. PFA the schematic for the switch and provide your feedback for the same.
I suggest please use of the adaptive bias features is shown in figure7.In some details see page12.http://www.analog.com/media/en/technical-documentation/data-sheets/AD8304.pdf
for AD8153 we'll verify and I'll get back to you.
In the datasheet it is given that :
"It is recommended that no I2C bus activity occurs when a conversion is taking place.
However, this may not be possible,for example, when operating in Mode 2 or the automatic cycle mode. In order to maintain the performance of the ADC in such cases, Bits D7 and D6 in the cycle timer register are used to delay critical sample intervals and bit trials from occurring while there is activity on the I2C bus. This may have the effect of increasing the conversion time."
Does this mean that the clock used in the automatic cycle mode during the conversion is provided by the on-chip oscillator of the A/D converter or the I2C clock is used for conversion? Please clarify.
In our design, the A/D converter samples data at time intervals fixed in the cycle timer register and does the conversion. In case the resultant data violates the limits set in limit register, the A/D converter sends the ALERT interrupt signal to the SoC which reads the out of limit data from the A/D converter through the I2C bus. How does the I2C clock of the SoC initiates to read the data? Does the A/D converter sends an initiation signal to the SoC to indicate start of data read or the SoC continously keeps on polling the data from the A/D converter? Kindly look into this and confirm how data transmission initiates through I2C?