AD7124-4 DOUT/RDY# PIN

Moreover the pin does not seem to change to RDY mode in single conversion mode and when CS_EN=1 and CS=1

The status register poll seem to work properly. But the pin isnt.

Hi, Kerem.

When /CS is taken high, the DOUT/ /RDY pin is tri-stated. Therefore, the DOUT/ /RDY pin will not indicate the end of the conversion.The user can determine the end of the conversion by reading the status register.

Thanks,

Jellenie

Hi Jellenie

"

By setting the CS_EN bit in the ADC_CONTROL register to 1, the change of functionality is controlled by the CS rising edge. In this case, the DOUT/RDY pin continues to output the LSB of the register being read until CS is taken high. Only on the CS rising edge does the pin change from a DOUT pin to a RDY pin. This configuration is useful if the CS signal is used to frame all read operations. If CS is not used to frame all read operations, set CS_EN to 0 so that DOUT/RDY changes functionality following the last SCLK edge in the read operation.

"

The above paragraph seems to describe a different behavior. If, when CS taken high, the DOUT pin becomes always tri state, then whats the point of saying "the pin will become RDY pin when CS taken high, provided that CS_EN is set to 1 in ADC_CONTROL register. How we can see RDY behaviour on a tri-state pin.

Thanks

Kerem

Hi, Kerem.

Sorry for confusion. When the CS_EN bit is set to 0, the DOUT/RDY pin changes from its DOUT function to its RDY function, following the last inactive edge of the SCLK. The above paragraph "When /CS is taken high, the DOUT/ /RDY pin is tri-stated. Therefore, the DOUT/ /RDY pin will not indicate the end of the conversion. The user can determine the end of the conversion by reading the status register. " is for CS_EN=0.  However, when CS_EN bit is set to 1, the DOUT/ RDY pin continues to operate as a DOUT pin after the SCLK inactive edge and pin changes function to a RDY pin when CS is taken high. Like what mentioned in the datasheet, this configuration is useful if the /CS signal is used to frame all read operations, if not then set CS_EN to 0.

Thanks,

Jellenie

Hi Jellenie,

I understand the part for CS_EN=0.

"...pin changes function to a RDY pin when CS is taken high"

The above says?? when CS_EN=1

Hi, Kerem.

Yes. When CS_EN=1, the change of functionality of DOUT/RDY pin from being a DOUT pin to a /RDY is controlled by the /CS rising edge. Do you have a screen shot of your digital lines when you set the CS_EN=1 and when you set CS_EN=0?

Thanks,

Jellenie

Hi Jellenie,

When I set CS_EN=1 and CS#=0 then RDY works as expected. On the CS rising edge the pin does not become RDY pin as indicated below.

"...pin changes function to a RDY pin when CS is taken high"

It becomes RDY pin when CS=0 regardless of CS_EN setting. CS rising edge makes the pin float which is obviously not a RDY indication.

I think the bold text need to be revised in the datasheet. To see the RDY function CS must be low. This may be included as a clarification as well.

Hi, Kerem.

Let me verify your concern and come back to you soon.

Thanks,

Jellenie

Hi, Kerem.

Apologies. The text is incorrect. When CS_EN is low, the DOUT/RDY pin changes from being a DOUT pin to a RDY pin a new nanoseconds after the last SCLK rising edge. When CS_EN is high, the DOUT/RDY pin will continue to output the LSB of the data being read until the CS pin is taken high. When CS is taken high, the DOUT/RDY pin is tri-stated. This will be corrected in the datasheet. Thank you so much for your feedback.

Thanks,

Jellenie