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ADAS3023 power sequence


according to the datasheet of ADAS3023 the power sequence must be as following (page 24):
There is a schematic on page 21 (Figure 38) where AVDD, DVDD and VIO coming up together since all those voltages connected to 5V.
My questions:

1.If it’s allowed that AVDD, DVDD and VIO appear together (Figure 38), what is the right time for VDDH and VSSH than? Before or after?
2.As I see in figure 38 both voltages (VDDH and VSSH) appearing simultaneously. Is it allowed for those both voltages?

Many thanks in advance.

Best Regards

  • Hi,


           I am checking on this, and get back to you shortly.



  • Hi VL39,

         I would recommend to follow the power up sequence from the datasheet. The ADAS3023 ahs a fundamental sensitivity in which the digital state of various circuit element in different supply interact. Like for example, if the logic which controls the front-end timing (PGIA,MUX,etc) starts up which is not synchronous to the state when the conversion happens, it will be possible that the part will not be responsive. As mentioned on page 24 of the datasheet, the power up sequence of the ADS3023. Below is the picture of the recommended power up sequence. It is also recommended to have a RESET pulse following a power up sequence, this will make the ADAS3023 in known state. Please refer to the PD and RESET timing requirement on figure 46 on page 26 in the datasheet. RESET must be applied after returning PD to low to restore the ADAS3023 digital core, including CFG register, to its default state and the user has to keep RESET low for another 100ns after PD release. Therefore, the desired CFG must be rewritten to the device and one dummy conversion must be completed before the device operation is restored to the configuration programmed prior to PD assertion.



  • Hello Jonathan and many thanks for your reply,

    Does it mean that you wouldn’t recommend the schematic in Figure 38? That schematic would be easier for us to realise because all three voltages are 5 volts.

    Thank you.

  • Can anyone tell me where Jonathan's illustration, with CNV high for > 200ns at least 200ns before the falling edge of the PD followed by a 100ns gap before a > 200s pulse on the RESET line, comes from? This is not in rev B of the ADAS3023 datasheet and is not consistent with ADAS3023 datasheet page 24 Figure 46. I have inherited some code that does make some references to these timings, but I would like to know where this comes from. Thanks!