AD7606-6 - Delay from Analog Input to Digital Output


I am DFAE from Phoenix Technologies in Israel.

One of my customers use the AD7606-6 for power metering application.

Their analog signal voltage level is +/-10V.

They don't use the internal LPF

They see delay between analog input to digital output with the analog signal from +/-1.5V and above.

The delay increased when the analog input voltage increased.

On  +/-1.5V the delay is ~2msec and on +/-10V the delay is ~14msec

Please advise if is it proper behavior of the part?

This delay is to large for them

Thanks a lot,


  • Hi meir,

    Can you share scope shots of your digital signals? What interface mode are you using?



  • Hi Mier,

            The AD7606 conversion is initiated  by CONVST. The rising edge of this pin initiates sampling and BUSY pin goes high  indicating that AD7606 is converting. The delay from start of conversion  until the data is available is the or falling edge of the BUSY pin is the conversion time. When the conversion is done ( falling edge of BUSY), the data can be read using the /CS and /RD pins (please refer to Digital Interface section of the Datasheet).

           The delay that you mentioned is from the time of sample and the digital output. They can check when the /CS and /RD signals falling edge occur or when are they start reading the data after CONVST rising edge. Another point to check also if they are using digital filters. When using digital filters, it will have variable conversion time depending on the OS ratio, although this very unlikely because it will only have 19us maximum delay.

          It also recommended to have the part reset after power up by pulsing a 50ns on the RESET pin. As mentioned from the previous comment, if you can share some digital data or the interface mode that they are using it can give us better understanding of the problem.



  • Hi Jonathan and Bing,

    Unfortunately I can't attached the files here, appreciate if you could share your email and I'll send them to you (I am DFAE of ADI at Phoenix Technologies in Israel).

    Please see the attached two pages with Schematics: 1-st page - ADCs, 2-nd - Amplifiers.

    I show below the fragment of one analog input amplifier:

    At the left you see the current input at the range: 0...40mA RMS (50Hz).

    At the right the differential voltage output: 0...6.634 V RMS (50Hz), 9.38V - amplitude.

    The problem is dependence of the delay into ADC on amplitude of the input signal.

    For example the difference between 6mA and 40mA input current may be up to 14 µsec - 15' (50Hz Sine).

    When we reduced the resistors of output filter: R65 & R230 to 100Ω, the delay was ~3 µsec.

    Please explain us this phenomenon.

    What can we do to improve this parameter?

    What the value of R65 & R230 you recommend?


    In the datasheet I paid attention to

    It means: is the canceling of R230 may cause to the offset error?

    Thanks a lot,


  • Hi Meir,

                   Please correct me if my assumption is wrong about the customer not using the internal LPF where the internal LPF refers to the Oversampling Digital filter.

                    Other than the Oversampling digital filter, the AD7606 has on chip anti aliasing filter ( a second order Butterworth). This analog anti aliasing filter is internal and from it has some phase delay which is about 10us to 14us. Looking on the figure 38 of the datasheet shows the Analog Antialias Filter phase response. Different voltage range have different phase delay. So the estimated overall delay after sampling for the AD7606 would be phase delay + conversion time + read time.



  • Hi Meir,

                The analog antialiasing filter is internal, so the customer always going to see the phase delay. Not using this filter is not an option for this part.

                Unlike the digital Oversampling filter, you can choose to use or not to use this filter.

                You may send some details through my email