Good morning all,
First post on these forums... Hoping somebody can help!
I've come across a bit of an issue using the Analog Devices AD7949 14-bit SAR ADC. I am interfacing with the device using SPI; however, it has just dawned upon me reading more through the timing details, that the devices does not have a dedicate chip select pin, but rather uses a 'CNV' pin - but which does not behave as a true chip select (usually active low) pin.
There are two other devices (completely different devices, with CS pins) on the bus; both of which I can communicate with just fine over the SPI bus, by driving the appropriate devices' CS pin low and transferring data over the bus, then deselecting the device by driving CS high again.
However, now - I haven't written the code to interface with the AD7949 yet - but it's looking like communication with the device is going to be problematic, as the SDO and DIN pins may or may not be set to a high impedance state. The only thing that makes me think the pins will be high impedance is page 25 of the datasheet "When CNV is brought low after EOC, SDO is driven from high impedance to the MSB. Falling SCK edges clock out bits starting with MSB − 1.".
However, that doesn't account for DIN - although page 28 "A rising edge on CNV initiates a conversion, forces SDO to high impedance, and ignores data present on DIN.". Which implies so long as CNV is high, DIN is ignored and SDO is high impedance. BUT - page 28 is referring to the read/write spanning conversion mode, which I am not using - as the host cannot fulfil the timing requirements in that mode.
Furthermore, page 24 says "the register [this is talking about the configuration register] can be written to during conversion, during acquisition, or spanning acquisition/conversion, and is updated at the end of conversion" - but nowhere does it state specifically CNV must be low to do so. So if I'm writing to other devices on the SPI bus, and CNV is high - I could potentially alter the contents of the CFG register in the ADC, without wishing to do so? BUT - all the timing diagrams show updating the CFG register only when the CNV pin is driven low. So - I don't think I do have a problem, but it's strange not to see specific words that confirm this...
END EDIT ----
EDIT 2 ----
Having just re-read the datasheet again and again, I've realised - page 2 says "When CNV is low, reading/writing can occur during conversion, acquisition, and spanning conversion, as detailed int he following sections". So I guess that sort of answers my own question, when CNV is high - DIN is ignored at all times!
END EDIT 2 -----
So, could anybody confirm the AD7949 can be used on a SPI bus with multiple other devices successfully? I've worked with SPI plenty before, it may be the wording that seems to be confusing me this time...
Many thanks in advance!
The AD7949 is SPI compatible device. Although the AD7949 does not use the conventional CS pin which is most of the time driven by a logic low digital signal to initiate a conversion. The AD7949 uses rising edge of CNV to initiate conversion, which is connected to SS, the DOUT is connected to SPIs MISO, DIN is connected to MOSI and SCK to SCK (kindly refer to figure 39 of the datasheet). I think the part can be connected to the SPI bus but it needs to use a rising edge on SS to CNV instead of conventional active low CS to initiate conversion.
May I know how many other SPI devices connected to the bus? If you could share maybe a block diagram on how you are planning to connect it so we can also have a better understanding of the problem.