AD7278 10 SCLK Cycle Serial Interface

Hi all,

I have a question about serial interface.

In the datasheet @ AD7278,

Figure 34. AD7278 Serial Interface Timing Diagram

Figure 35. AD7278 in a 10 SCLK Cycle Serial Interface

1.

The t3 specification is none @ Figure35 in a 10 SCLK Cycle Serial Interface.

Is it correct ?

2.

If it is correct ,

"t3 : Delay from CS until SDATA three-state disabled" is 0 ns(max) ?

In other words, at the same time CS is Low, SDATA becomes three-state disabled ?

Of course, I'll only have to satisfy the requirement of 6 ns (min) for t2 : CS to SCLK setup time.

Best regards,

sss