AD7278 10 SCLK Cycle Serial Interface

Question

Hi all, 
 I have a question about serial interface. 
 In the datasheet @ AD7278, 
 Figure 34. AD7278 Serial Interface Timing Diagram 
 Figure 35. AD7278 in a 10 SCLK Cycle Serial Interface 
 1. 
 The t3 specification is none @ Figure35 in a 10 SCLK Cycle Serial Interface. 
 Is it correct ? 
 2. 
 If it is correct , 
 "t3 : Delay from CS until SDATA three-state disabled" is 0 ns(max) ? 
 In other words, at the same time CS is Low, SDATA becomes three-state disabled ? 
 Of course, I'll only have to satisfy the requirement of 6 ns (min) for t2 : CS to SCLK setup time. 
 Best regards, 
 sss

jcolao · Accepted Answer

Hi sss, 
 The timing specification on table 5 is applicable on AD7276/AD7277/AD7278 unless it is otherwise noted that it is only on a specific part. The T3 which is 4ns(min), although not mentioned on figure 35, it is also applicable in the 10 SCLK Cycle Serial Interface. 
 Regards, 
 Jonathan