AD7173-8 and multiple channel sampling

Hi everyone, I am trying to use AD7173-8 in an application where 3 channels are to be used and I am a little confused about that.

In particular:

  • The AD7173-8 is connected to a microcontroller via SPI. I have configured SPI according to the datasheet and communications are OK. The SPI clock frequency that I am currently using for tests is 2 MHz and I intend to push it further, if necessary. Data read from the ADC are seen on the DOUT/~RDY pin of the ADC.
  • ADC configuration details:
    • Only 3 channels of the ADC are enabled; the rest are disabled on power-up.
    • ADC MODE:SING_CYC bit is set, mode: continuous conversion, delay after channel switch: 0 us
    • IF MODE / DATA STAT: enabled for testing
    • Two setups are used (0 and 1); in setup 0, output is offset binary and in setup 1 output is unipolar.
    • Two filter configurations are used (0 and 1); in FILTCON0, sinc5+sinc1 is used and ODR is 10417 samples/s - in FILTCON1, sinc3 is used and ODR is 20.01 samples/s (this is for sampling a temperature sensor output that does not change fast)
    • External reference (ADR4533, +3.3 V) is used and external buffers (AD8572) are placed between analog voltages and ADC, thus input buffers are disabled; clock is provided by an external crystal at 16 MHz
  • The microcontroller reads the data register of the ADC at regular time intervals (upon overflow of a timer).
  • Having only one channel enabled, everything works OK. I can read data into the microcontroller's registers and they correspond to the known analog voltage values that are present each time. I read 3+1 = 4 bytes (3 with data and 1 with the contents of the STAT register).
  • When I try to enable two channels, I read 2x(3+1) = 8 bytes that correspond to successive readings of the data register. I notice that, when stepping through the microcontroller's code, the first 4 bytes correspond to one of the two ADC channels and the remaining 4 are rubbish (0xFFs); however, the STAT register contents indicate that sometimes one channel is read, sometimes the other.

What I want to do is to have a consistent way of reading all enabled channels of the ADC. The datasheet says about the DOUT/~RDY pin that goes low to indicate that a conversion has been completed. Up to now, when hooking a 'scope to check logic levels on the SPI lines, I cannot see DOUT/~RDY going low right after an SPI transaction; it remains high and then it goes Hi-Z (green trace is ~CS, yellow trace is DOUT/~RDY):

Has anyone a suggestion to move forward? What exactly should I have to do to switch channels fast enough without losing data?

Parents
  • Dear Jellenie, thanks for your reply; however, the DOUT/~RDY pin does not get LOW at all, as you can see in the 'scope screenshot in my post. After ~CS goes HIGH to end the SPI transaction, DOUT/~RDY stays HIGH, then apparently goes Hi-Z as the quasi-exponential voltage drop suggests. Have I done anything wrong in configuring the AD7173-8?

    EDIT: The above is not correct.

    In fact, the DOUT/~RDY line does get LOW "sometimes" but not at the rate that I expect (225 us with 10417 sps ODR). I changed the SPI clock up to 10 MHz and the sampling rate (= the timer overflow rate) up to 8 kHz but I could not get the desired result.

    I played with SPI clock frequencies and sampling rates and filter ODRs but I could not have a DOUT/~RDY waveform where that line gets LOW right after ~CS gets HIGH at the end of a transaction.

    Here is a screenshot from a test where only CH0 is active with ODR=31250 samples/s, the sampling rate has been set to 40 kHz and the SPI clock frequency to 5 MHz. The yellow trace is ~CS and the green trace is DOUT/~RDY; I had to play with the 'stop' button of the digital storage 'scope to see that:

    Please help me understand how this nice ADC works by commenting on the following statements:

    1. In continuous conversion mode, the state of DOUT/~RDY must be checked and a new sample should be read when it gets LOW.
    2. SPI clock frequency must be as high as possible with the available hardware in order to avoid loss of data.
    3. Data reading must be synchronized in some way with the channel switching that occurs inside the AD7173-8. (how can that be done?)

    I just read this thread and started thinking about the same thing... is that what you would suggest?

Reply
  • Dear Jellenie, thanks for your reply; however, the DOUT/~RDY pin does not get LOW at all, as you can see in the 'scope screenshot in my post. After ~CS goes HIGH to end the SPI transaction, DOUT/~RDY stays HIGH, then apparently goes Hi-Z as the quasi-exponential voltage drop suggests. Have I done anything wrong in configuring the AD7173-8?

    EDIT: The above is not correct.

    In fact, the DOUT/~RDY line does get LOW "sometimes" but not at the rate that I expect (225 us with 10417 sps ODR). I changed the SPI clock up to 10 MHz and the sampling rate (= the timer overflow rate) up to 8 kHz but I could not get the desired result.

    I played with SPI clock frequencies and sampling rates and filter ODRs but I could not have a DOUT/~RDY waveform where that line gets LOW right after ~CS gets HIGH at the end of a transaction.

    Here is a screenshot from a test where only CH0 is active with ODR=31250 samples/s, the sampling rate has been set to 40 kHz and the SPI clock frequency to 5 MHz. The yellow trace is ~CS and the green trace is DOUT/~RDY; I had to play with the 'stop' button of the digital storage 'scope to see that:

    Please help me understand how this nice ADC works by commenting on the following statements:

    1. In continuous conversion mode, the state of DOUT/~RDY must be checked and a new sample should be read when it gets LOW.
    2. SPI clock frequency must be as high as possible with the available hardware in order to avoid loss of data.
    3. Data reading must be synchronized in some way with the channel switching that occurs inside the AD7173-8. (how can that be done?)

    I just read this thread and started thinking about the same thing... is that what you would suggest?

Children
No Data