Hi everyone, I am trying to use AD7173-8 in an application where 3 channels are to be used and I am a little confused about that.
What I want to do is to have a consistent way of reading all enabled channels of the ADC. The datasheet says about the DOUT/~RDY pin that goes low to indicate that a conversion has been completed. Up to now, when hooking a 'scope to check logic levels on the SPI lines, I cannot see DOUT/~RDY going low right after an SPI transaction; it remains high and then it goes Hi-Z (green trace is ~CS, yellow trace is DOUT/~RDY):
Has anyone a suggestion to move forward? What exactly should I have to do to switch channels fast enough without losing data?
Dear Jellenie, thanks for your reply; however, the DOUT/~RDY pin does not get LOW at all, as you can see in the 'scope screenshot in my post. After ~CS goes HIGH to end the SPI transaction, DOUT/~RDY stays HIGH, then apparently goes Hi-Z as the quasi-exponential voltage drop suggests. Have I done anything wrong in configuring the AD7173-8?
EDIT: The above is not correct.
In fact, the DOUT/~RDY line does get LOW "sometimes" but not at the rate that I expect (225 us with 10417 sps ODR). I changed the SPI clock up to 10 MHz and the sampling rate (= the timer overflow rate) up to 8 kHz but I could not get the desired result.
I played with SPI clock frequencies and sampling rates and filter ODRs but I could not have a DOUT/~RDY waveform where that line gets LOW right after ~CS gets HIGH at the end of a transaction.
Here is a screenshot from a test where only CH0 is active with ODR=31250 samples/s, the sampling rate has been set to 40 kHz and the SPI clock frequency to 5 MHz. The yellow trace is ~CS and the green trace is DOUT/~RDY; I had to play with the 'stop' button of the digital storage 'scope to see that:
Please help me understand how this nice ADC works by commenting on the following statements:
I just read this thread and started thinking about the same thing... is that what you would suggest?