AD7173-8 and multiple channel sampling

Hi,

When multiple channels are enabled, a complete settling time is required for every channel switch. This is to allow the digital filters and modulator to settle when switching channels. Thus, the rate at which data is available (DOUT/RDY pulls low) for multiple channels would be dependent on the corresponding settling time for the output data rate(ODR) set. Please see table 19-21 on the AD7173-8 datasheet for the complete list of settling time. The user must then read the conversion result while the ADC converts the next enabled channel; otherwise, the new conversion result is lost. So, it is really recommended to monitor the DOUT/RDY pin to check if valid conversion is available. Can you stop reading back the conversions and just monitor the DOUT/RDY pin to determine if it is pulsing at the corresponding settling time?

Thanks,

Jellenie

Dear Jellenie, thanks for your reply; however, the DOUT/~RDY pin does not get LOW at all, as you can see in the 'scope screenshot in my post. After ~CS goes HIGH to end the SPI transaction, DOUT/~RDY stays HIGH, then apparently goes Hi-Z as the quasi-exponential voltage drop suggests. Have I done anything wrong in configuring the AD7173-8?

EDIT: The above is not correct.

In fact, the DOUT/~RDY line does get LOW "sometimes" but not at the rate that I expect (225 us with 10417 sps ODR). I changed the SPI clock up to 10 MHz and the sampling rate (= the timer overflow rate) up to 8 kHz but I could not get the desired result.

I played with SPI clock frequencies and sampling rates and filter ODRs but I could not have a DOUT/~RDY waveform where that line gets LOW right after ~CS gets HIGH at the end of a transaction.

Here is a screenshot from a test where only CH0 is active with ODR=31250 samples/s, the sampling rate has been set to 40 kHz and the SPI clock frequency to 5 MHz. The yellow trace is ~CS and the green trace is DOUT/~RDY; I had to play with the 'stop' button of the digital storage 'scope to see that:

Please help me understand how this nice ADC works by commenting on the following statements:

1. In continuous conversion mode, the state of DOUT/~RDY must be checked and a new sample should be read when it gets LOW.
2. SPI clock frequency must be as high as possible with the available hardware in order to avoid loss of data.
3. Data reading must be synchronized in some way with the channel switching that occurs inside the AD7173-8. (how can that be done?)

I just read this thread and started thinking about the same thing... is that what you would suggest?

Hi,

1. In continuous conversion mode, the ADC converts continuously and when /CS is low the DOUT/RDY pin goes low each time a conversion is complete. So it is really important to monitor the DOUT/RDY pin or the /RDY bit in the status register and start reading the conversion as soon as it goes low. The /RDY pin is reset high when a read operation is complete and remains high until the next conversion is complete.

2. Yes, sufficient number of SCLKs must be provided and the SCLK rate must be fast enough so that a read is completed before the next conversion result and to avoid losing data.

3. When several channels are enabled, the ADC automatically sequences and performs conversion through the enabled channels. But then again, the DOUT/RDY pin pulses low each time the conversion is complete. So, just like the thread that you have mentioned you can monitor the DOUT/RDY pin and use it as an interrupt to the microcontroller to read a conversion result. 

Thanks,

Jellenie

Thank you, Jellenie; I have started trying out the approach you suggested.

I was intending to use a falling edge external interrupt on MISO (DOUT/~RDY) line as a trigger for SPI transactions. However, that did not work. Instead, careful study of the code presented here revealed that the external interrupt must be triggered when DOUT/~RDY is LOW. This is what I did and I managed to read data from the ADC.

The following screenshots shows DOUT/~RDY (yellow trace) and DIN (green trace) while having 2 channels activated; SPI clock frequency is 5 MHz:

A. reading data with ODR=31250 SPS (notice that SING_CYC=1 in my case, therefore the actual sampling rate is 6.2 kHz)

B. this is what happens before starting sampling - even when I disconnect the ADC from the microcontroller after setup. Notice the pulses on DOUT/~RDY line, each one of apprx. 9 us duration.

C. Here is an short excerpt from raw data transferred over USB. Again, two channels are activated (CH0 and CH2); data in bold correspond to the contents of the DATA_STAT register and the 3 bytes on the left of each byte in bold are the contents of the corresponding channel (0 or 2), showing that the ADC continuously reads the activated channels in a circular manner.

... AE 4E C3 02 B4 55 97 00 AE 4E 8F 02 B4 56 C6 00 AE 4E FB 02 B4 55 93 00 AE 4E EC 02 B4 53 86 00 AE 4E 95 02 B4 51 0B 00 AE 4E C3 02 B4 55 97 00 AE 4E 8F 02 B4 56 C6 00 AE 4E FB 02 B4 55 93 00 AE 4E EC 02 B4 53 86 00 AE 4E 95 02 B4 51 0B 00 ...

I am currently developing my host PC application where data captured from USB are logged into a text file for further processing.

Hello again, I have managed to get correct readings from two channels of the AD7173-8 ADC to my microcontroller...

However, I want to read all activated channels in a consistent order, always starting from channel with the lowest number. For example, having CH0 and CH2 activated, I want to start reading always with CH0 first.

In my microcontroller program, I enable the external interrupt for DOUT/~RDY right after enabling the channels I want and configuring the ADCMODE register (address 0x01). Is there anything I can use so that I ensure the activated channels are always read in the order described above? Please share any ideas you might have.