Post Go back to editing

ad7323 DOUT valid


I am implementing a verilog component to interface to the ad7323 adc. I am having trouble figuring out when to sample DOUT in relation to the SCLK. Reading the timing diagram and Pin Function Descriptions confuses me.

Based on the above description i am lead to believe that i need to sample on the rising edge because DOUT changes on the falling edge!? Based on the properties of SPI this do not make sense since DIN and DOUT is clocked (and then latched) out on opposite edges.

The unambiguous description below is taken from the ad5724 datasheet and would be exactly the description i would expect to be valid for the ad7323 adc as well.

Best regards