I have an AD5641 running at 5V supply, controlled by a 3.3V SPI line at 20MHz clock rate. (30 MHz are allowed according to datasheet). A sum of a small 100kHz sine wave ( 20 to 40mV Vpp) and a DC offset has to be generated. A bigger signal at 100kHz would approach the DAC's specified slew rate, so I can't test at higher amplitudes.
In the midscale the sine wave looks acceptable (small negative spikes present between bits, but they are cought well enough by the reconstruction filter - see picture below). Once I start adding a DC offset to it, some bits of the sine start to spike out:
I've dumped a large chunk of control data using a logic analyzer and used an SPI decoder to plot the data - it contains a perfect sine as expected, the SPI analyzer did not have any problems decoding any frames. The SPI lines are about 5cm long, about 75 ohm with a 75-ohm series termination enabled in the fpga.
Here is a screenshot of a single frame to ensure my SPI implementation is within spec:
Any idea what I am missing?The specified DNL doesn't seem to allow spikes that high. Is a glitch like this allowed during the internal register update?