A problem about the internal Vref Of AD7667

Hello!

I am now using an AD7667  conversion chip, and I use  the internal reference voltage, the parallel model, but my output has been FF7F, through inspection , I found that the internal reference voltage on the pin of REF is about 0.3V, this means there is something wrong with the internal reference voltage. But my PD, PDREF PDBUF is low, SER/PAR set to high (that is in parallel model), using the model of IMPULSE . 

And after many inspections ,I am sure the circuit ,pin-strap,and the chip of AD7667 are all good.So what's the problem?

Thanks for your help

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  • 0
    •  Analog Employees 
    on Sep 9, 2016 12:30 AM over 4 years ago

    Hi Liang,

    Okay, well if you're confident that the board and components are not the issue, there are a couple more things you can try to get closer to the answer.  The REF and REFBUF are only influenced by the components connected to their respective output pins and the logic pins PDREF and PDBUF.

    The first I can think of is to replace those 10k pull down resistors with shorts to ground to force that node to always be 0V.  I have no reason to believe your current scheme wouldn't be doing this, but at the very least it will rule this out.

    Another approach would be to set PDREF high to power down the reference and drive REFBUFIN with an external source.  Try driving the pin to 1.2 V.  Make sure PDREF is high when you do this though to ensure the reference is shut down.  This can also be done to the reference buffer output by shutting down the reference buffer (PDBUF set high) and driving the REF pin to 2.5 V.  See if you can get any performance under these conditions.

    -Tyler

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  • 0
    •  Analog Employees 
    on Sep 9, 2016 12:30 AM over 4 years ago

    Hi Liang,

    Okay, well if you're confident that the board and components are not the issue, there are a couple more things you can try to get closer to the answer.  The REF and REFBUF are only influenced by the components connected to their respective output pins and the logic pins PDREF and PDBUF.

    The first I can think of is to replace those 10k pull down resistors with shorts to ground to force that node to always be 0V.  I have no reason to believe your current scheme wouldn't be doing this, but at the very least it will rule this out.

    Another approach would be to set PDREF high to power down the reference and drive REFBUFIN with an external source.  Try driving the pin to 1.2 V.  Make sure PDREF is high when you do this though to ensure the reference is shut down.  This can also be done to the reference buffer output by shutting down the reference buffer (PDBUF set high) and driving the REF pin to 2.5 V.  See if you can get any performance under these conditions.

    -Tyler

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