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AD7608 Lockup problem... Very rare

We use AD7608 and AD7606 in a number of designs. Very rarely (every 6 months) a converter will stop functioning normally. When the converter stops working it produces a continuous stream of zero values across all channels. A valid reset pulse without removing power will restore the converter to full operation.

I suspect that we are glitching the reset line with pulses much shorter than the data sheet specified minimum (we have very high vacuum voltages exceeding 40kV in our system and we experience occasional high voltage arcs in our system which cause noise throughout the system). Arcs are rare, and the vast majority do not cause any troubles in the system, so we have no hard evidence of a cause and effect... but all of our other electrical issues always seem to boil down to arc susceptibility.

Does anyone have any experience with getting an AD7608 or AD7606 into a bad state with poor reset pulses? 

  • Hi,

       I am looking in to this. I'll get back to you soon.



  • Hi Jeff-at-zeiss,

       The way I understand your problem is that, the AD760x ADC stops working by producing a zero on the data output and suspected a glitch on the reset line that causes the ADC to have an unwanted reset or malfunction. Having a 40kV in the application as you mentioned, a glitch would likely to occur and the hard part is that these are unpredictable. I haven't got experience this phenomenon yet.

          If the glitch is the suspect, I can suggest putting some glitch protection circuit in the application. There is an ADI ADG5462F, user define fault protection and detection.. This will limit the glitch level and as well as cut the time of the glitch. I say time because the glitch could occur like a reset pulse and could be suspected as a reset. You can refer to the ADI website for details of the part.



  • Hi Jcolas:

    I have further observations and comments:

    I did manage to get the AD7608 to lock-up with glitches on the reset line. By coupling into the line with a capacitor driven from an arbitrary waveform generator I could simulate glitches of any desired width and observe the output data.

    For my particular AD7608 in my particular circuit layout, the ADC reliably executes resets down to a pulse width of about 12nsec (excellent margin from the datasheet spec of 50nsec minimum). The ADC functions normally every time coming out of resets of this width.

    At 9nsec the part never executes any resets, but keeps working normally. It just doesn't see them at all.

    But at about 10.7nsec the part sometimes resets normally, sometimes does not reset at all (but keeps running normally) , and sometimes locks-up... meaning that it will only produce zero output samples on all channels in response to CONVST  pulses. One caveat is that I am not monitoring the BUSY signal so it could be that the part is never responding to the CONVST at all and might possibly be diagnosed as broken by monitoring the BUSY signal. My design does not monitor the BUSY signal so I have not investigated what it does during lock-up.

    When the ADC locks-up, a valid reset of at least 50nsec always brings it back to normal operation.

    So we are implementing two different correction strategies...  slow down and decouple the reset line, and issue a valid reset pulse whenever channels are reading zero that are never expected to read zero. 


  • HI Jeff,

       Thank you for your feedback. As mentioned on the datasheet reset should be 50ns. But as you observed it will go to reset even at 12ns but at ~10ns it will not have a good behavior. I'll talk with the collogues here and get back to you.



  • Hi Jeff,

       In the actual application, it will be difficult to predict when the glitch would occur and in the situation an invalid reset would happen. To ensure that ad7608 is in a known and a valid conversion happen, a valid reset should occur prior to conversion. In this sequence, it expected that after a force reset the AD7608 is in a known state and that the next conversion is valid.



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