AD7691 spec sheet says Common-Mode Range needs to be Vref/2 +-0.1V.
I have a system who's inputs to the ADC is In-=0.1V In+=1.4V(up to 1.8V), and I don't see any issues due to this.
Can someone help me understand when this specification is important.
My guess is that it has to due with the input voltage range and max input voltage. Is this spec just to ensure a full range (+-Vref) signal stays within the absolute input voltage range?
Thanks in advance,
Correct! Common-Mode Range should be within Vref/2 +-0.1V. To ensure within the absolute input voltage.
see answer to my question. I had similar issue
Understanding common mode voltages with true differntial ADC
Basically linearity of the ADC degrades outside the common mode spec
AD7691 is a true differential ADC and not a good choice for your application.You probably need a pseudo-differential ADC.
Reduce redesign risk with correct ADC analogue input
Understanding Single-Ended, Pseudo-Differential and Fully-Differential ADC Inputs - Application Note - Maxim
Follow up question. I have a sensor that varies from 1.4V to 1.8V dc signal, a AD7691 running at about 70kSPS with a 2.5V Vref ADR361. I see steps in the converted output that occur every 39.1mV(2048LSBs) with a magnitude of 8-16LSBs. This is what I have tried to resolve this:
1) Buffering Vref with a AD8031, not effect. I don't think this would have helped because the ave current draw of off the ADC should be close to 8-10uA.(ad7691 spec says 60uA with 5V ref at 250kSP, this current should scale down with Vref voltage and sample rate)
2) Fixing Connection from Vref to Vdd, this removed stuck bits.
3) Increasing Reference capacitor value from 1uF to 10uF, this reduced noise but not steps.
4) Center the sensors common mode to Vref/2 per AD7691 spec, This had no effect on steps.
I think the problem has something to do with the ADC since the steps occur every 2048LSBs. I measured the ADCs transient effects(similar to AN931) and it shows there is a settling time of a few mS but no major oscillations.
1) Is my current estimate above close?
2) Can the average supply current change as the ADC input increases? How much?
3) What am I missing here?
The reference must be capable of supplying the average current needed to top up the reference capacitor without causing the reference voltage to droop significantly. Insufficient drive strength is an issue, especially if low-power references or micro power reference buffers are used, as these typically have much higher output impedances that increase dramatically with frequency. Have you consider using either the ADR4525 or ADR431 as an alternative to the ADR361? To avoid conversion errors, the average current required at a particular throughput should not cause the reference voltage to droop more than 1/2 LSB. It’s critical to place a 10uF (eg. 0805, X7R) decoupling capacitor as close as possible to the REF pin of the ADC using wide traces to connect it.
Which ADC driver are you using to drive the AD7691 inputs? The latest low power, low noise ADA4807-1 would be a good candidate to consider for the ADC driver. The RC filter between the ADC driver output and SAR ADC input does two-fold tasks: Attenuates kick-back coming from capacitive DAC input of the SAR ADC and also reduces noise coming from the upstream analog front end, so it's important to choose the right RC values (see figure 29) to achieve optimum performance. It is best to choose a capacitance value of 1nF to 3nF (NPO types) and a reasonable resistance value that will keep the ADC driver stable. Distortion increases with both input frequency and source resistance (see figure 31). The sensor common-mode should be set to Vref/2 as you have done.
Refer to these Analog Dialogue articles for more details.
Hope that helps.
Thanks for the reply, and the references they helped a lot.
I am using a ADR361(2.5V) reference, the conversions are bursted at about 50kSPS; AD7691 draws 60uA @250kSPS & 5V ref, I estimated this will cause a 2.2uV error on Vref(<1/2LSB). Hopefully my estimates here are correct, I have not measured it.
The AD7691 inputs will be buffered with a ADA4805, the Iqq/low noise and low offset drove this choice.
The 2 suggested Vrefs draw too much Iqq &/or have to large packages. I believe the ADR 361 is okay.
I believe the steps were causes by the sample/hold kickback and lack of recovery in time for the next conversion. I have tested 1 circuit with a dramatic reduction in step size. I will be testing a better circuit in the next few days.