Questions about AD7172/5/7-2

Hi.

1. Yes, since the AD7175 has a cross point multiplexer which selects any analog input combination that can be configured as an input pair, either single ended or fully differential. But please make sure that the analog input voltage should be within specifications. 

2. No, for a single channel, the settling time is required for the first conversion then all subsequent conversions occur at the selected output data rate. When multiple channels are enabled the settling time is required for the very first conversion and all the subsequent conversions requires a slightly shorter time than the first settling time. So let say for example AD7175 at ODR of 100sps using Sinc5+Sinc1 filter, the Tsettle at first conversion is 10.01ms and the Tsettle at subsequent channels will be 10ms. To visualize, you can try our Virtual Eval Tool. It is a tool that lets you play with the various features and see the performance of various ADCs online including timing. 

3. Yes, you can use separate reference for two measurements, just configure your necessary reference selection through software code.

Thanks,

Jellenie

4. What is current to the input, if it is not connected to a sampling channel (multiplexer us open)?

5. Assume I make a psudo differntial measurement mentioned in question 3b. The Ain+ connected to the signal and Ain- normally to the ground. What happens if the voltage on Ain- sinks below 0 V due to a disturbance?

6. What happens to the channels between sampling?

Hi, HAW.

Just a clarification on question number 2. If you have only one channel selected at 100sps, the effective ODR is 100sps or 10ms throughput time. If you have 2 channels selected, and both set to 100sps then the effective ODR is 50sps or 20ms throughput time. The reason for this is that it takes 10ms to sample first channel and another 10ms to sample the second channel. Again, the Virtual Eval Tool will help you on this.

4. We only have measured data for the analog inputs connected to the mux and this can be seen on the specification table in the datasheet. This value represent the worst case typical input current that the sensor will see. May I know what is your application? and why do you need to look at this specification?

5. With the analog input buffer disabled, the absolute minimum input voltage limit  on any of the analog input pins is AVSS - 0.05V, with the analog input buffers enabled the absolute minimum input voltage limit is AVSS. When the input voltage exceed this value, the ADC will still function but the part will not meet the datasheet specifications. Another consideration is that if the analog inputs are taken outside the allowable operating range the register settings may also become corrupt. Most importantly if the analog inputs beyond the Absolute Maximum Ratings of -0.3 V to AVDD1 + 0.3 V (table 3)  the AD7175-2 may cause permanent damage to the device.

6. When multiple channels are enabled, the ADC automatically sequences through the enabled channels and performs conversion. The ADC does not sample all channels simultaneously. When all channels have been converted, the sequence starts again with the first channel. The channels are converted in order from lowest enabled channel to highest enabled channel. The DOUT/RDY goes high during the start of conversion and goes low as soon as the conversion is available, then the ADC selects the next enabled channel and begins conversion. As soon as each conversion is available, the result (data) register is updated and the /RDY output pulses low. Therefore you have to read the first channel before the completion of the conversion of the next channel. The rate at which data is available (DOUT/RDY pulls low) for multiple channels would be dependent on the corresponding settling time for the output data rate(ODR) set. You can set the DATA_STAT bit in the interface mode register is to 1 so the contents of the status register, along with the conversion data, are output each time the data register is read. The status register indicates the channel to which the conversion corresponds. 

Thanks,

Jellenie

Hi Jellenie

6 b) I made an error in the formulation of the original question. I meant to ask what happens to analog inputs (that are assigned to a channel) between sampling? In which state are they?

The ADC is going to be used in test & measurement of the lithium batteries, some of them as small as 10 µAh with charging/disharging currents down to 1 µA. The currents into the ADC could manifest as unaccounted charging/discharging currents. Thus it is crucial to exactly understand what currents at which moments of time are flowing to the ADC, which   is  the purpose of Q6 in conjunction with Q4. For example I guess that the  30 nA is the current during sampling, and it should be significantly less when the mux is open. But that exactly the problem that I have to guess. 

I need to know for sure and kindly ask to answer the questíons 4 and 6 b) as precise and detailed as possible.

Thanks

Hi,

In relation to the input bias current when the inputs are connected to the mux during sampling the typical input current is of the order of 30nA typical. When the inputs are not being sampled, the input pin is connected to a switch internally in the ADC Mux, which is in the off position, and the other side of the switch connects to the Mux output. The current in an unselected input will be much less than 30nA typ, typically in the order of 5nA, as I mentioned previously we don’t have a lot of data gathered on this, so unfortunately we don’t have a plot to show. Also another thing to note is that the leakage will be temperature dependent.

Thanks,

Jellenie

7. What are the formulas to calculate gain from gain coefficient and offset code from offset voltage?

8. What are exactly "internal" and "system" calibration? what is the difference? How exactly are they performed. The datasheet is not clear enough.

especially

System calibrations, however, expect the system zero-scale (offset) and system full-scale (gain) voltages to be applied to the ADC pins before initiating the calibration modes. As a result, errors external to the ADC are removed.

Is confusing and vague and does not give clear instruction what should be done.

9. what purpose is "((AVDD1 − AVSS)/5)" setting in the input selection?

10. Do I suppose correctly that in unipolar mode the resolution is effectively equals 23 bit?

Hi,

7. The following equations show the calculations used in each calibration mode. The ideal relationship that is not taking account the ADC gain error and offset errors are as follows:

For unipolar: Data= [((0.75*VIN/VREF)*(2^23))-(Offset-0x800000)]*[(Gain/0x400000)*2]

For bipolar: Data= [((0.75*VIN/VREF)*(2^23))-(Offset-0x800000)]*[(Gain/0x400000)+0x800000]

These are shown on page 40 of  AD7172-2 datasheet. Please refer to it for further discussion.

8. In internal-calibration mode, the ADC determines the calibration points (gain and offset) internal to the ADC, thus you don't need to apply any external inputs as the calibration occurs internally. At internal offset, the selected positive analog input pin is disconnected, and both modulator inputs are connected internally to the selected negative analog input pin. 

On the other hand, the system calibration allows the converter to compensate for external system gain and offset errors, as well as its own internal errors. Thus, it expect the system zero-scale (offset) and system full-scale (gain) voltages to be applied to the ADC pins. From an operational point of view, treat a calibration like another ADC conversion. An offset calibration, if required, must always be performed before a full-scale calibration.

To start a calibration, write the relevant value to the mode bits in the ADC mode register. The DOUT/RDY pin and the RDY bit in the status register go high when the calibration initiates. When the calibration is complete, the contents of the corresponding offset or gain register are updated, the RDY bit in the status register is reset, the DOUT/RDY pin returns low (if CS is low), and the AD7172x reverts to standby mode.

9. This (AVdd-AVss)/5 feature is used to monitor the supply voltage. For this feature to work on the AD717x the user needs to ensure that the analog input buffers are enabled and that +/-(AVdd-AVss)/5  inputs are selected together. 

10. The number of effective resolution will depends on the selected output data rate and filter used. Please refer to table 20-24 of AD7172-2 datasheet.

Thanks,

Jellenie

Hello Jellenie,

At first a general note, I ask question that about what I could not understand from the data sheet. It is not helpful when you simply copy-paste from it, like you did with questions 7 and 8. Perhaps you just don't know the answer? Or you could ask a clarifiying question if I you don't understannd, what I am asking about.

7. So how do I calculate offset (register) from offset voltage and gain from the gain coefficient?

I would like clear separate formulas Offset=? and Gain=?

8.I need more information about system calibration. Do the voltages have to be applied to both pins? Do they need to be physically applied or the inputs could be simplöy switch to ground for offset calibration and to reference voltage for gain calibration? 

10. I see I used "effective" somewhat misleadingly. What I really asked about is the unipolar mode mentioned on page 24. It says the format is straight binary, but I suspect that it is achieved by making it 2's complement and ignoring the - the negative range and thus the MSB, thus reducing the real resolution by 1 bit. Am I correct?

Thank you for your help

Hello,

7. Actually you can derive the equation that you are asking from the above equation. But first, I would like you to understand how the calibration coefficients affects the conversion results. Sorry for not giving a detailed explanation regarding the formula above. But the signal flow can be viewed as

[Input Signal] -> [PGA] -> [Attenuation by 0.75] -> [ADC Conversion] -> [Subtract Offset] -> [Scale by FS/0x400000] -> [Data Register].

This shows that 1 LSB of the offset register is equivalent to approximately 1.3 LSB of the data register, assuming the nominal full-scale coefficients are present. The exact value varies slightly from part to part, and the ratio changes if the
full-scale register coefficients are modified. The exact ratio can be derived by dividing the value in the full-scale register by 0x400000. This gives a value close to 1.33 with the nominal full-scale coefficient of 0x555555. But if the full-scale register is modified by the user, the ratio changes. This occurs since the offset removal is performed before the gain scaling when the ADC is adjusting the converter output. The full-scale register can be interpreted as a multiplication factor, whose value equals (full-scale coefficient/0x400000.) Since the scaling is done after the offset register is removed, the relative weight of an offset register LSB is different to a data register LSB. The nominal value of 1.3 for the gain scaling is because the input signal is  attenuated by 3/4 as part of the ADC conversion. A 4/3 scaling is then required to digitally compensate for this. (This is normally transparent to the user; it’s only when manipulating calibration values that this can become apparent.)

So for example, you have a known offset voltage and you want to calculate the offset register for a given nominal full-scale coefficient of 0x555555. Let assume you have a known input voltage VIN, of course VREF is also given. Data value will be equal to expected output code without the offset error. So using the equation below you can now calculate the required offset register value to compensate for a known offset voltage.

For unipolar: Data= [((0.75*VIN/VREF)*(2^23))-(Offset-0x800000)]*[(Gain/0x400000)*2]

                     Offset = [((0.75*(VIN+offset voltage)/VREF)*(2^23))-((Data*0x400000)/(Gain*2))]-0x800000

Regarding the full-scale coefficient or full-scale calibrations, it is a simple scaling coefficient, so to increase the gain of the ADC by 10%, the full-scale coefficient needs to be increased by 10%.

8. For system calibration, like the data sheet mentioned it expect the system zero-scale (offset) and system full-scale (gain) voltages to be applied to the ADC pins. So for a system zero scale, usually the selected AIN+ and AIN- are shorted together and bias to a certain voltage which is usually midscale or half VREF. For a system full scale, the full scale voltage (i.e. VREF) is applied to the selected AIN+ and AIN- input pins.

10. No, In unipolar the output code is natural (straight) binary with a zero differential input resulting in a code of 00..00, a midscale of 100..000, and a full-scale of 111...111.

Thanks,

Jellenie