Questions about AD7172/5/7-2

Hi, HAW.

Just a clarification on question number 2. If you have only one channel selected at 100sps, the effective ODR is 100sps or 10ms throughput time. If you have 2 channels selected, and both set to 100sps then the effective ODR is 50sps or 20ms throughput time. The reason for this is that it takes 10ms to sample first channel and another 10ms to sample the second channel. Again, the Virtual Eval Tool will help you on this.

4. We only have measured data for the analog inputs connected to the mux and this can be seen on the specification table in the datasheet. This value represent the worst case typical input current that the sensor will see. May I know what is your application? and why do you need to look at this specification?

5. With the analog input buffer disabled, the absolute minimum input voltage limit  on any of the analog input pins is AVSS - 0.05V, with the analog input buffers enabled the absolute minimum input voltage limit is AVSS. When the input voltage exceed this value, the ADC will still function but the part will not meet the datasheet specifications. Another consideration is that if the analog inputs are taken outside the allowable operating range the register settings may also become corrupt. Most importantly if the analog inputs beyond the Absolute Maximum Ratings of -0.3 V to AVDD1 + 0.3 V (table 3)  the AD7175-2 may cause permanent damage to the device.

6. When multiple channels are enabled, the ADC automatically sequences through the enabled channels and performs conversion. The ADC does not sample all channels simultaneously. When all channels have been converted, the sequence starts again with the first channel. The channels are converted in order from lowest enabled channel to highest enabled channel. The DOUT/RDY goes high during the start of conversion and goes low as soon as the conversion is available, then the ADC selects the next enabled channel and begins conversion. As soon as each conversion is available, the result (data) register is updated and the /RDY output pulses low. Therefore you have to read the first channel before the completion of the conversion of the next channel. The rate at which data is available (DOUT/RDY pulls low) for multiple channels would be dependent on the corresponding settling time for the output data rate(ODR) set. You can set the DATA_STAT bit in the interface mode register is to 1 so the contents of the status register, along with the conversion data, are output each time the data register is read. The status register indicates the channel to which the conversion corresponds. 

Thanks,

Jellenie

Hi, HAW.

Just a clarification on question number 2. If you have only one channel selected at 100sps, the effective ODR is 100sps or 10ms throughput time. If you have 2 channels selected, and both set to 100sps then the effective ODR is 50sps or 20ms throughput time. The reason for this is that it takes 10ms to sample first channel and another 10ms to sample the second channel. Again, the Virtual Eval Tool will help you on this.

4. We only have measured data for the analog inputs connected to the mux and this can be seen on the specification table in the datasheet. This value represent the worst case typical input current that the sensor will see. May I know what is your application? and why do you need to look at this specification?

5. With the analog input buffer disabled, the absolute minimum input voltage limit  on any of the analog input pins is AVSS - 0.05V, with the analog input buffers enabled the absolute minimum input voltage limit is AVSS. When the input voltage exceed this value, the ADC will still function but the part will not meet the datasheet specifications. Another consideration is that if the analog inputs are taken outside the allowable operating range the register settings may also become corrupt. Most importantly if the analog inputs beyond the Absolute Maximum Ratings of -0.3 V to AVDD1 + 0.3 V (table 3)  the AD7175-2 may cause permanent damage to the device.

6. When multiple channels are enabled, the ADC automatically sequences through the enabled channels and performs conversion. The ADC does not sample all channels simultaneously. When all channels have been converted, the sequence starts again with the first channel. The channels are converted in order from lowest enabled channel to highest enabled channel. The DOUT/RDY goes high during the start of conversion and goes low as soon as the conversion is available, then the ADC selects the next enabled channel and begins conversion. As soon as each conversion is available, the result (data) register is updated and the /RDY output pulses low. Therefore you have to read the first channel before the completion of the conversion of the next channel. The rate at which data is available (DOUT/RDY pulls low) for multiple channels would be dependent on the corresponding settling time for the output data rate(ODR) set. You can set the DATA_STAT bit in the interface mode register is to 1 so the contents of the status register, along with the conversion data, are output each time the data register is read. The status register indicates the channel to which the conversion corresponds. 

Thanks,

Jellenie