Post Go back to editing

# AD7625 data sheet (Quick question: AD7961 in the self-clocked mode )

Hello,

This is my first post. I have a few quick questions about the AD7961 in the self-clocked mode:

1)  If you are using AD7961 in the self-clocked mode can you adjust the clock frequency?

2) In my application, I would prefer to use the self-clock mode but the typical clock period is 4 ns, does the ADC always run at this clock speed ?

3) I calculated the maximum frequency it is found to be around 8ns if you do the calculation in Table 3 note1 which would be perfect. Does the ADC adjust the clock frequency based on the time between conversions?

The reason why I asking is because the digital host's IOs is not fast enough to accommodate the AD7961 (max 160Mbit/s). So another option would be is to run the ADC in echoed clock mode, if I subtract tCYC from tCLKL for the maximum case I get 160ns for 16 bits this would yield a 100 Mhz clock. Would that be sufficient to clock out the data from the ADC running a 5 MSPS ( I am designing for  5 MSPS but actually running at 4 MSPS at the moment) .

Samuel

• Hi Samuel,

1)  If you are using AD7961 in the self-clocked mode can you adjust the clock frequency? Yes, However the minimum CLK Frequency is 1/(( tcyc - tMSB + tCLKL)/n).

2) In my application, I would prefer to use the self-clock mode but the typical clock period is 4 ns, does the ADC always run at this clock speed ? You should be able to adjust clock period to 4nS and run the clock typically 250MHz to capture the data from ADC.

3) I calculated the maximum frequency it is found to be around 8ns if you do the calculation in Table 3 note1 which would be perfect. Does the ADC adjust the clock frequency based on the time between conversions? The time between conversion spec dictate the throughput and the min clock frequency would be around 112.5Mhz(or 8.89ns Max clock period) in a  self-clocked mode based on the calculation shown in footnote 1 of Table 3.

The reason why I asking is because the digital host's IOs is not fast enough to accommodate the AD7961 (max 160Mbit/s). So another option would be is to run the ADC in echoed clock mode, if I subtract tCYC from tCLKL for the maximum case I get 160ns for 16 bits this would yield a 100 Mhz clock. Would that be sufficient to clock out the data from the ADC running a 5 MSPS ( I am designing for  5 MSPS but actually running at 4 MSPS at the moment) . You should be able to run the AD7691 at 5MSPS with a  100MHz clock in the echoed clock mode.

regards,

Lloben

• This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

Thank you,