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AD7793 output clamped to all zeros

Hey guys. 

I'm trying to include analog devices CN0326  pH-measuring circuit in an already existing measuring circuit controlled by an MSP430. 
For now, I have removed the isolator (ADum5401) because it rendered my LED display in an unpowered state. But this shouldnt affect any signals, since it only isolates between two digital areas. 

Anyhow, the problem at hand is, that the adc only outputs zeroes. 
I have solid SPI communication with the chip, and I can update and read from registers without any issues. I'm running on a very low bus-speed just to make sure my problems aren't SPI related (allthough I haven't ruled that out 100% yet). 

I start my software like so: 

Read ID register (I get the correct value) 

Internal fullscale calibration 

Internal zeroscale calibration

Set the mode register (Idle mode, 64kHz internal clk and 4.17Hz update rate). 

Set the config register (bipolar, Gain 1, buffered mode, ch1)   

I read both mode and config register back, and the correct values are stored. 

Then a lot of other stuff happens (regarding the other circuit) and when its time to convert, I change the mode reg to a single conversion, the config register to the fitting channel (Ch1 for pH, Ch2 for temperature). 

I'm supposed to measure ph in a -420 mV to 420mV span, but right now, I have tried every kind of voltage and configuration and I still can't get a conversion. 

I might not have configured it correctly even once. At this point I kinda blinded myself by trying so many different things. 

So for a +-420 mV range, how should i configure the adc with bias voltages, references etc etc. 

If you need any more info, please let me know. 

Parents
  • Hi again. 

    I believe I pulled CS low, yes. And yes, i can read back the exact values i put in X register. Aswell as reading the right ID. 

    Unfortunately i havent got the controller, only the frontend. 

    I placed the ad in continuous mode in main, and in the loop I hardcoded the control of CS with a delay to give clear signals. The following came out: 

    The first picture is CS on probe 1 and DOUT/RDY on probe 2. This is at 4.17Hz conversion rate.

    The second picutre is the same, except this time with 50Hz conversion rate. 

    The pulses visibly change without a doubt, but there a spikes / blanks that I can't explain. The loop only calls a few eeprom functions, but that only explain irradical behavior when CS is low. Other than that, there are calculations and display routines and the hardcoded CS handling. Thats it. 

    In my setup I only need to run single conversion about once every second. So i tried to configure some tests for that. 

    The following shows the exact same setup as before, only this time the convertion function is called in the loop and not in main. Thus it is called once every second. I originally thought i had the handling on CS secured, but now I'm not so sure. In the following pictures probe channel 2 is always DOUT/RDY!! : 

    (1).The picture shows CS on probe 1. It looks quite similar to the first picture from continuous conversion, there is only pulse. Which makes sense. In this routine there is a delay (2.5 mil clk cycles) to ensure proper signals. After the delay i read the data register. I'm not sure i can make sense of the DOUT signals. I tried to look at the corresponding CLK and it showed nothing similar to 3x8 CLK signals. It looks like I'm not reading properly from the data register, but I should be, since I use the same function to read fx the mode register. The address and number of bytes are just different. 

    (2) The two pictures above show a read of the status register, AFTER a conversion is done. Again, I have a long delay to make sure of this, and I also confirmed with the scope that DOUT goes low accordingly. The output of the status register gives me a value of 72, or 0x68 which equals a high error flag. 

    And we just made sure the analog values were usable. I have no idea what to make from this. What is causing my error? 

    (3) The 2 pictures above show the exact same setup as in (2), except here, I have no delay of 2.5 mil cycles. First picture shows DOUT and CLK, second one shows DOUT  and DIN. The CS acts just like before. And this is where I'm really confused. The first CLK pulses are 32 pulses, which suggests a data register read of all 1's. However, the corresponding signal on DIN is not equal to 0x58 and the read value I show on my display is 0.0000. 

    I hope this gives you some more info to work with.

    If you need anymore tests done, could you please suggest several things for me to try out?
    If it is one response a day from each of us, I prefer them to be long and full of info. Otherwise it's too much downtime for me.

    Really appreciate your help. Thanks!  

Reply
  • Hi again. 

    I believe I pulled CS low, yes. And yes, i can read back the exact values i put in X register. Aswell as reading the right ID. 

    Unfortunately i havent got the controller, only the frontend. 

    I placed the ad in continuous mode in main, and in the loop I hardcoded the control of CS with a delay to give clear signals. The following came out: 

    The first picture is CS on probe 1 and DOUT/RDY on probe 2. This is at 4.17Hz conversion rate.

    The second picutre is the same, except this time with 50Hz conversion rate. 

    The pulses visibly change without a doubt, but there a spikes / blanks that I can't explain. The loop only calls a few eeprom functions, but that only explain irradical behavior when CS is low. Other than that, there are calculations and display routines and the hardcoded CS handling. Thats it. 

    In my setup I only need to run single conversion about once every second. So i tried to configure some tests for that. 

    The following shows the exact same setup as before, only this time the convertion function is called in the loop and not in main. Thus it is called once every second. I originally thought i had the handling on CS secured, but now I'm not so sure. In the following pictures probe channel 2 is always DOUT/RDY!! : 

    (1).The picture shows CS on probe 1. It looks quite similar to the first picture from continuous conversion, there is only pulse. Which makes sense. In this routine there is a delay (2.5 mil clk cycles) to ensure proper signals. After the delay i read the data register. I'm not sure i can make sense of the DOUT signals. I tried to look at the corresponding CLK and it showed nothing similar to 3x8 CLK signals. It looks like I'm not reading properly from the data register, but I should be, since I use the same function to read fx the mode register. The address and number of bytes are just different. 

    (2) The two pictures above show a read of the status register, AFTER a conversion is done. Again, I have a long delay to make sure of this, and I also confirmed with the scope that DOUT goes low accordingly. The output of the status register gives me a value of 72, or 0x68 which equals a high error flag. 

    And we just made sure the analog values were usable. I have no idea what to make from this. What is causing my error? 

    (3) The 2 pictures above show the exact same setup as in (2), except here, I have no delay of 2.5 mil cycles. First picture shows DOUT and CLK, second one shows DOUT  and DIN. The CS acts just like before. And this is where I'm really confused. The first CLK pulses are 32 pulses, which suggests a data register read of all 1's. However, the corresponding signal on DIN is not equal to 0x58 and the read value I show on my display is 0.0000. 

    I hope this gives you some more info to work with.

    If you need anymore tests done, could you please suggest several things for me to try out?
    If it is one response a day from each of us, I prefer them to be long and full of info. Otherwise it's too much downtime for me.

    Really appreciate your help. Thanks!  

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