I am diagnosing noise on a legacy design that has an AD7862 ADC. Typical signal is 2 to 5 Hz sinusoid. Sample rate is ca 7500 Hz. Problem is that converted digital signal is affected by at least +/- 5% by the sample rate. If I do an FFT I see the sinusoid peak and I see the 7500 peak about 20% of the former's magnitude. Otherwise very clean. ADC has 100 nF cer bypass cap to Vcc. Vref has 100 nF to ground. Vb1 = Vb2 = AGnd. /CS = AO = DGnd. Not sure what is wrong with this setup, but the noise is unacceptable.
Could you please provide the following:
These should help diagnose your problem. It's possible that the bandwidth of your driving amplifier is too low or your RC is not allowing enough time to settle the kick from the ADC sampling cap (even if your input signal is very slow).
Am I correct in saying that you are not using the multiplexers, but permanently sampling on VA1 and VA2?
Thanks for looking at this. Attached are:
- Part of schematic. What is shown as VA2 input is not used, and has
been physically swapped with VA1. So, VA2 is driven by PGA204.
- Net digital signal from VA2 plotted. FFT plotted. Spurious peak
around 7500 Hz.
- The U41 /CONST signal, also very close to 7500 Hz.
On Tue, Apr 4, 2017 at 4:33 AM, AFrost <
Okay. Removing the odd 100 nF capacitor from Vref to Vb1 & Vb2 cleans up the signal nicely.
So it sounds like switching noise from the unused analog input was being coupled onto the ref cap. These pins to ground should be as physically distant from each other as possible with a clean path to the ground plane of the PCB for the ref cap.
Can we say this issue is closed?
Sorry. I have been quite busy. Would you kindly take a look at this
excerpt of my report? The problem persists. I spoke with the consultant
who designed this, and he said, 'oh, yes, there is some quantization
noise. What do you expect?' But this is NOT quantization noise.
Michael L Anderson