About AD7276 Timing

Hi,

I would like to use AD7276.

I have three questions about AD7276 Timimg.

#1  If the falling edge of CS and the rising edge of SCLK are at the same time, is the behavior of AD7276 unstable?

#2  Given the SPI mode (eg mode 3), should SCLK after 14sclk(16sclk) be kept high until the next conversion?

#3   Is there a time definition of the question mark part of the attached diagram?

Best Regards,

Yuya

Parents
  • Hi, jcolao

    Thank you for answering!

    I will try to move it according to the timing of Datasheet.

    Although my customer's application, the application is a coin identification device.

    Apart from the request to use 3 Msps, 12 bit ADC, I have not heard anything more detailed, I do not know the timing etc details.

    Best Regards,

    Yuya

Reply
  • Hi, jcolao

    Thank you for answering!

    I will try to move it according to the timing of Datasheet.

    Although my customer's application, the application is a coin identification device.

    Apart from the request to use 3 Msps, 12 bit ADC, I have not heard anything more detailed, I do not know the timing etc details.

    Best Regards,

    Yuya

Children
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