About AD7276 Timing

Hi,

I would like to use AD7276.

I have three questions about AD7276 Timimg.

#1  If the falling edge of CS and the rising edge of SCLK are at the same time, is the behavior of AD7276 unstable?

#2  Given the SPI mode (eg mode 3), should SCLK after 14sclk(16sclk) be kept high until the next conversion?

#3   Is there a time definition of the question mark part of the attached diagram?

Best Regards,

Yuya

  • 0
    •  Analog Employees 
    on Apr 21, 2017 1:45 AM

    Hi Yuya,

       Please see answers below:

       

    #1  If the falling edge of CS and the rising edge of SCLK are at the same time, is the behavior of AD7276 unstable?

          As shown in the diagram Fig 31, there is a time t2 (set up time) requirement between CS falling and SCLK falling edge. When both CS falling  and SCLK rising occur at the same time, the result cannot be guaranteed. It is recommended to follow the timing shown in the datasheet.

    #2  Given the SPI mode (eg mode 3), should SCLK after 14sclk(16sclk) be kept high until the next conversion?

    the SCLK can be continues, with the SCLK going high it can be easier to control the timing of the next conversion.

    #3   Is there a time definition of the question mark part of the attached diagram?

    No. that time was not define.

       

    What is the application that you are creating need changes in the timing? If you can share some details we could assist you on some ways.

    Regards,

    Jonathan

  • Hi, jcolao

    Thank you for answering!

    I will try to move it according to the timing of Datasheet.

    Although my customer's application, the application is a coin identification device.

    Apart from the request to use 3 Msps, 12 bit ADC, I have not heard anything more detailed, I do not know the timing etc details.

    Best Regards,

    Yuya