AD7091R-4 Malfunctioning

Hi,

 

I am validating a design using a AD7091R-4 ADC and some errors are coming up. This component has been used in 12 boards, and all 12 of them are showing the same problem. Might it be due to a faulty batch?

 

When the system is turned ON it might happen that the ADC works correctly or it starts outputting wrong values and transitioning to wrong channels, and won't stop failing, this error sometimes is fixed when rebooted.

 

The ADC is routed as shown below, and when is working properly outputs the data shown in the next figure. Which correspond to the ADC working in normal operation, with channels 0,1 & 2 selected, followed by the value of configuration and channel registers.

When it boots failing, the output is as shown below . Sometimes the channel sequence is correct , but the values never are in all three. The value is allways right in channel 0 (reference voltage), and sometimes in channel 2, but hardly ever in channel 1. Even the configuration and channel registers output a wrong value sometimes.

A SW reset is performed at boot time with 66 convst pulses,  then write in every register, set the sw reset bit, and then read all the registers (shown below).

Any ideas why it might show this behaviour? 

Thank you in advance

Parents
  • Hi ,

    Thank you for your answer.

    Below are the scope shots of system.

    This is VDD at channel2 and convs at channel1. as can be seen VDD is at 3.3V 8 seconds before reseting the ADC. VDRIVE rises to 1.8V at the same time as VDD.

    Here is CONVST and VDD in detail

    And here CONVST and VDRIVE.

    The entire 66 CONVST pulses at reset.

    And CONVST in detail. There is 2.5 us between pulses.

    Is there any more shots you would like to see?

    Thanks you

    Best regards

Reply
  • Hi ,

    Thank you for your answer.

    Below are the scope shots of system.

    This is VDD at channel2 and convs at channel1. as can be seen VDD is at 3.3V 8 seconds before reseting the ADC. VDRIVE rises to 1.8V at the same time as VDD.

    Here is CONVST and VDD in detail

    And here CONVST and VDRIVE.

    The entire 66 CONVST pulses at reset.

    And CONVST in detail. There is 2.5 us between pulses.

    Is there any more shots you would like to see?

    Thanks you

    Best regards

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