AD7091R-4 Malfunctioning

Hi,

 

I am validating a design using a AD7091R-4 ADC and some errors are coming up. This component has been used in 12 boards, and all 12 of them are showing the same problem. Might it be due to a faulty batch?

 

When the system is turned ON it might happen that the ADC works correctly or it starts outputting wrong values and transitioning to wrong channels, and won't stop failing, this error sometimes is fixed when rebooted.

 

The ADC is routed as shown below, and when is working properly outputs the data shown in the next figure. Which correspond to the ADC working in normal operation, with channels 0,1 & 2 selected, followed by the value of configuration and channel registers.

When it boots failing, the output is as shown below . Sometimes the channel sequence is correct , but the values never are in all three. The value is allways right in channel 0 (reference voltage), and sometimes in channel 2, but hardly ever in channel 1. Even the configuration and channel registers output a wrong value sometimes.

A SW reset is performed at boot time with 66 convst pulses,  then write in every register, set the sw reset bit, and then read all the registers (shown below).

Any ideas why it might show this behaviour? 

Thank you in advance

  • Hi, & ,

    Sorry to bother but I'm running out of ideas. Any chance you have heard about a similar case o could guess why it is showing this behaviour?

    Thanks you

    Best regards

  • 0
    •  Analog Employees 
    on May 16, 2017 6:21 PM

    Hi Husein,

    Can you share scope shots on the digital interface?to gives us more information.Seems the part is not properly reset.  Just to confirm the reset delay of atleast 10nS once VDD and Vdrive reach 2.1V as shwon in figure53.

    regards,

    LLoben

  • Hi ,

    Thank you for your answer.

    Below are the scope shots of system.

    This is VDD at channel2 and convs at channel1. as can be seen VDD is at 3.3V 8 seconds before reseting the ADC. VDRIVE rises to 1.8V at the same time as VDD.

    Here is CONVST and VDD in detail

    And here CONVST and VDRIVE.

    The entire 66 CONVST pulses at reset.

    And CONVST in detail. There is 2.5 us between pulses.

    Is there any more shots you would like to see?

    Thanks you

    Best regards

  • Hi, & ,

    Just wanted to let you know that it seems that it was indeed a faulty batch after all. After great effort isolating the random failure, I replaced the AD7091R-4 IC for a new one (#1410 27222 serie has been replaced by #1707 39311), and after 200 power ups it seems to be working just fine.

    Thank you for your help.

    Best regards

  • 0
    •  Analog Employees 
    on Aug 31, 2017 2:37 PM

    Hello Husein and all

    I'm debugging this same part for a customer, it may be a bit late, if you don't mind I post it here so others may benefit from this thread.

    As far as I'm aware, there is no issues with the part or batch numbers. The Reset pin needs to be properly control.

    From your schematic the reset pin is permanently tie high via a resistor !.  Ideally it should  also be tied to a microprocessor where it can issues a reset in the form of a pulse (i.e. high-Low-high) in order to reset the IC just after power-up. 
    The reset 'pulse width' and the reset 'pulse delay' should comply to our specification. see fig. 43 and Table 2, of the AD7091R-4 Data Sheet Rev.C.
     

    After the power up and reset it by pulsing it, from here you may use the soft reset (SRST) see table 16. Please note using this Software reset function will resets the internal digital control logic and the result and alert registers, but it does not reset the other memory map registers.

     

    Alternatively as your hardware stands, your only option now is to use the power-on devices initialization method as described in page 33 of the data sheet Rev.C. which you are trying to do from your plots. However from looking at your convst signal graph it appears half a cycle out.  The Convst signal should be default high at all times and should pulse as and when required from high-low-high. Try default high your Convst signal at all times unless starting to pulse it.

    Also if  you start the Convst signal low and then pulsing it,  in order to start a conversion please note your half cycle out (delayed) as the Convert Start Input Signal is Edge triggered logic input. The falling edge of CONVST places the track-
    and-hold mode into hold mode and initiates a conversion.

     

    Great if you can send me a higher resolution of the above screenshots and a Convst signal for a start convert case.

     

    Regards,

    Ching