ADAS1000-3/4 CE Electrode Operation

Hi Rajaram,

Thanks for message.

1. In single ended mode, any electrode can be applied to any input, with the output of the ADC = ECG input - CM amp output. The CM amplifier output can be configured to whatever you want, typically this would be WCT.

In digital lead mode, a lead calculation is performed after the ADC, the digital lead calculation is fixed, so CH1 = ECG1 - ECG3, CH2 = ECG2-ECG1 and CH3 = ECG2-ECG3. Therefore depending on what you are referencing the V lead too, the digital lead mode may/may not be suitable.

2. It's not intended to change operational modes on the fly. While you would not need a reset in between changing modes, there might be some settling as the channel changes to another mode, this would likely be seen as a disturbance in the ADC results.

3. The Shield driver is not expected to drive much current, it's just biasing the shield of the cable. The RLD drive is similar, it's not intended to drive much current either, also, it will be driving the patient, so there will always be an external patient protection resistor in series to limit the current pushed into the patient as dictated in the medical standards.

best regards,

Catherine.

Thanks Catherine,

Does Shield drive and RLD drive same ( derived from same source)? We have seen with our experiment using RLD as shield provides better immunity to noice issues. Also, there need to be certain current ( may be in nA) to drive these shiels, it cant be just a voltage reference. You may like to verify this.

Thanks 

Rajaram

Hi Rajaram,

The RLD amplifier is designed to drive the patient RL electrode. The function of this block is to close the loop around the patient, which helps with common mode rejection. You have a choice as to how you use the RLD Amplifier.

1. You can drive it with the CM_OUT (yellow in drawing) via an external RIN resistor. The CM_OUT comes from the Common mode amplifier, this can be any combination of the ecg inputs, you configure this in the CMREFCTL register (bits 19:23).
2. You can drive it again from the ECG electrodes, but this time internally and without the need for the external RIN resistor (Blue Path). You have full control of each of the SWs, so can configure to what you need using the CMREFCTL register (bits 9:14)

Note the positive terminal of the RLD block is connected to the internal VCM_REF = 1.3V, when using the RL electrode, the patient gets driven to 1.3V, this effectively centers the ecg channel inputs into the middle of the ADC input range.

The Shield amplifier is designed to drive the shield of the cable. The input to the shield amplifier is always the output of the common mode block, this can be any combination of the ecg inputs, you configure this in the CMREFCTL register.

If you could share some detail on your application, how you have the device configured and what your expectations are, that would be helpful to understand. I guess i don't understand what you are trying to do, what you are seeing that makes you use the RLD drive the shield....

best regards,

Catherine.

Hi Catherine,

Thanks for the clarifications, we are busy evaluating the EVM hence took time on this. I have few more questions

1. Planning to use ADAS1000-4 and ADAS1000-2 as gang mode operation in our solution ( as per Table 17 of ADAS1000 datasheet). Configuring these IC for common electrode ( RA) mode and derive 12 lead ECG ( I, II, V1', V2', V3', V4', V5' and V6'). As suggested in Fig-57 of ADAS1000 datasheet. 

We wanted to test this configuration on ADAS1000 EVM ( PN# 08-036248, Rev C, with bottom label 15640-13). We know that the EVM has ADAS1000 and ADAS1000-2 on it, but we wanted to try  above mentioned configuration ( Using ADAS1000 as ADAS1000-4). But we couldn't get any data out from the device. EVM works fine when we use single chip mode ( using ADAS1000 master IC only), and configure for 3-leads acquisition ( dont care for other two inputs).

But why the same doesn't work when we use both the ICs in Gang mode while master IC is configured to receive inputs ( I, II and V1') and slave IC ( V2', V3',V4',V5'V6')? I am puzzled.

I have attached the registor dump with this post (https://drive.google.com/drive/folders/0BzijZ7g34FUNU0JzUV96QXdCbFk?usp=sharing) . Appreciate your help to understand this better.

Regards

Rajaram Shastri.

Hi Catherine,

Any update on this? We need to know the results of this , as our design implementation is struck. Can you please verify at the earliest.

Regards

Rajaram