1. How does the serial interface operate?
The serial interface on these families of converters is implemented as a state machine. The interface works by counting clocks on each data transfer. Therefore…
The serial interface on these families of converters is implemented as a state machine. The interface works by counting clocks on each data transfer. Therefore, if you are performing a write operation to one of the ADC’s 16-bit registers, 16 SCLK cycles must be applied to the ADC, and the converter will transfer in the 16 bits of data on the DIN line on each of the sixteen SCLK cycles. When this operation is complete, the part returns to a state in which it expects the next operation to be a write operation to the communications register. This happens regardless of which register has been accessed and whether a read or write operation has taken place. The ADC knows how many clock cycles should be in a transfer to/from a particular register and in this way knows when the transfer is complete. The first bit of the communications register is a gating bit that must be set to 0 to access the communications register. If there is a 1 on the DIN line when the part is expecting a write to this bit, the part effectively wraps itself around to monitoring that bit. If there is a 0 on the DIN line when the part is expecting a write to this bit, the part continues to load the next seven bits of the communications register on the next seven SCLK cycles.
The serial interface on these converters consists of four signals: /CS, SCLK, DIN, DOUT/RDY. The DIN line is used for transferring data into the on-chip registers while the DOUT/RDY line is used for accessing data from the on-chip registers. SCLK is the serial clock input for the device and all data transfers (either on DIN or DOUT/RDY) occur with respect to this SCLK signal. The DOUT/RDY pin operates as a data ready signal also, the line going low when a new data-word is available in the data register. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the output register to indicate when not to read from the device. This is to ensure that a data read is not attempted while the register is being updated. /CS is used to select the device. It can be used to decode the individual converters in systems where a number of parts are connected to the serial bus. The serial interface can operate in 3-wire mode by tying the /CS input low. In this case, the SCLK, DIN, and DOUT/RDY lines are used to communicate with the converter. This scheme is suitable for interfacing to microcontrollers. If /CS is required as a decoding signal, it can be generated from a port bit. For microcontroller interfaces, it is recommended that the SCLK idle high between data transfers.
The converters can also be operated with CS used as a frame synchronization signal. This scheme is suitable for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by /CS since /CS would normally occur after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers provided the timing numbers are obeyed.
2. What is the recommended initialization sequence?
On power-up, it is advisable to perform a reset by writing consecutive ones to the part. The number of 1s to be written will vary from part to part (32 for AD779x, AD7780/81, AD7788/89/90/91, AD7170/71, 40 for AD719x, 64 for AD717x and AD7124). This will reset the serial interface, and it will also reset the on-chip registers to their default conditions. The device does have a power-on reset function. However, any glitches during power-up can cause corruption of the registers, so a reset in the initialization routine is advisable. After the reset, the device can be configured for the application. Each channel to be used in the application should be selected in turn, the operating conditions for that channel selected (gain, reference source), and the channel calibrated. For parts that contain sequencers, only one channel should be enabled when the calibrations are being performed. So, the user needs to enable each channel separately and, with the reference, gain, etc set for the channel, perform the calibration (zero-scale and full-scale).
3. Are there any precautions that should be taken to make the interface more robust?
The interface implementation on these converters is basically a state machine that counts clock pulses and defaults to waiting for a write to the communications register when an operation is complete. When the communications register is written to, specifying a write to the mode register, for example, the ADC knows that number of SCLK pulses that are required to clock in the data. Spurious clocks on the interface cause the interface to lose synchronization, leading to wrong registers being addressed and thereby corrupting the interface. Tying DIN high between write operations prevents invalid data being written to the ADC.
The first bit in the write operation to the communications register is a gating bit that must be 0 to allow the remaining seven bits to be clocked into the register to specify the next operation. To avoid the possibility of interface issues due to spurious clocks, it is advised to take the DIN line of the converter to a logic high as soon as each write to the converter is complete. Since these converters default to waiting for a write to the communications register, taking DIN high when it has completed a sequence prevents invalid data being written to the communications register if spurious clocks occur. At this time, the ADC is waiting for a 0 on DIN before it enables further data into the register. If the part is set up for a write to the communications register with the DIN high, it is effectively immune to spurious serial clocks. This will not prevent spurious clocks received during a write operation from corrupting the interface.
4. If the interface does get corrupt, what are the options to regain control of the ADC? Writing a number of consecutive ones to the interface (32 for AD779x, AD7780/81, AD7788/89/90/91, AD7170/71, 40 for AD719x, 64 for AD717x and AD7124) will reset the serial interface into a known state where the ADC is waiting for a write to the communications register. This resets the interface and all of its internal registers to their power-on reset values.
On the AD7124 and AD717x families, /CS can be used to reset the interface also. When /CS is taken high, the serial interface is reset to the idle state i.e. it returns to the state where it is waiting for a write to the communications register. Any read or write operations being performed are abandoned. So, if a write operation is being performed when /CS is taken high but the ADC has not received the required number of SCLK pulses to complete the write operation, the write operation is abandoned and the appropriate register is not updated.
5. How do I interface to multiple ADCs over the same serial interface?
A single microcontroller/DSP can be used to communicate with several ADC devices. The /CS input of the ADC can be used to enable or disable the serial interface of the ADC. By controlling the /CS inputs to the ADCs using a decoder, the microcontroller/DSP can communicate with each ADC individually or simultaneously. The following figure shows the interface between a microprocessor and several ADCs. The /CS input of each ADC is connected to the decoder. Using the decoder, the microprocessor can select the ADC with which it wants to transfer data/ instructions. When /CS is high, the serial interface of the ADC is disabled and it ignores any activity on the data bus. To communicate with the ADC, its /CS line can be taken low. The ADC will then have access to the data bus between itself and the microprocessor. The data sheet should be consulted for timing specifications.
6. When reading from the ADC, only the first read after power-up is successful. All subsequent read operations give invalid results. What could be happening?
It is probable that the digital interface is entering an unexpected state following the read operation. When using the digital interface of the ADC, it is critical that the correct number of SCLK cycles is provided when reading from or writing to the control registers. If one extra clock cycle is provided and a write operation is then attempted, the part will enter an unexpected state. Similarly, if less than 16 clocks are provided when reading from a 16-bit register, the interface will lose synchronization. Another probable cause is spurious clocks on the SCLK line. The first bit of any write to the communications register is a 0. The ADC will ignore bus activity until it receives a 0. If DIN is left low after performing a read, any spurious clocks on the SCLK line will clock a bit into the communications register. The next time that eight bits are written to the communications register, only the first seven bits will be loaded, and the eighth bit will be interpreted as the first bit of a subsequent write. This problem can be avoided by pulling DIN high after each write.
If the /CS line is being used as a frame synchronization signal, ensure that this line is brought high at the correct time. Also ensure that the correct number of clock pulses have occurred before /CS is brought high. If the interface does lose synchronization, writing consecutive number of ones (32 for AD779x, AD7780/81, AD7788/89/90/91, AD7170/71, 40 for AD719x, 64 for AD717x and AD7124)) into the device will reset the interface and the on-chip registers to their power-on values.
7. When single conversion mode is used, can /CS be taken high after the single conversion is initiated?
The serial interface is independent of the sampling process. So, once the single conversion is initiated, the ADC will power up and perform the single conversion irrespective of the /CS polarity. So, the user can take /CS low, initiate the single conversion and then take /CS high again. When the conversion is complete, /CS can be taken low to read the conversion and another single conversion can be started if required. When /CS is taken high, the DOUT/RDY pin is tristated. Therefore, the DOUT/RDY pin will not indicate the end of the conversion. The user can determine the end of the conversion by reading the status register. Alternatively, the conversion time could be timed out by the microcontroller clock.
8. When information (conversion data or information from the on-chip registers) is read from the ADC, the LSB read back is always 1. Why?
The DOUT and RDY functions share a pin on the ADC. So, the DOUT/ RDY pin functions as a ready pin when /CS is low. Every time a conversion is completed, the pin goes low, indicating to the microprocessor that a valid conversion is available. When the user requests a read of the data register, the DOUT/RDY pin functions are a DOUT pin. When pulses are applied to the SCLK pin, the data is placed on the DOUT pin. The data is output from the ADC following the SCLK falling edge and is valid on the SCLK rising edge. When the LSB of the data is placed on the DOUT/RDY pin, the DOUT/RDY pin changes its functionality so that it operates as a RDY pin. The change from the DOUT to the RDY function occurs on the last SCLK rising edge. The microprocessor is latching the bits on the SCLK rising edge. So, if the microprocessor is slow, then the DOUT/RDY pin is functioning as a RDY pin when the LSB is latched into the microprocessor. So, the microprocessor reads the value of the RDY pin rather than the LSB, causing the LSB to be a 1. To prevent this, a faster microprocessor must be used. Alternatively, general-purpose input/output pins of the microprocessor can be used to represent a serial interface. By bit-banging, the user has more control over the read instant. By reading the values on the DOUT pin when SCLK is low rather than latching in the data on the SCLK rising edge, all bits of the data read will be valid.
For the AD7124 and AD717x families, the instant at which the DOUT/RDY pin changes from being a DOUT pin to a RDY pin is programmable. For the AD7124 parts, setting the CS_EN bit in the ADC_CONTROL register to 1 forces the DOUT/RDY pin to continue outputting the LSB until the SCLK rising edge. The AD7124 also has an option to delay the instant at which the DOUT changes function by 100 ns using the DOUT_RDY_DEL bit in the ADC_CONTROL register. The DOUT_RESET bit on the AD717x parts performs the same function as the CS_EN function on the AD7124. These features ensure that the processor reads the LSB.
9. What is the \SYNC pin and how do I use it? Can I leave this open when unused?
The \SYNC pin can be used to initiate the start of conversion. When this pin is taken low, the modulator and filter are held in a reset state without affecting any of the setup conditions of the part. When \SYNC is taken high, the ADC begins sampling/starts conversion which allows the user to start gathering samples at a known point in time which is very useful in functional safety applications where timing needs to be controlled.
The \SYNC pin also allows synchronization of the digital filters and analog modulators when using multiple ADC devices. To synchronize multiple ADCs, the master clock for all devices must be the same. So, the same external clock could be applied to all the ADCs, or alternatively one device could output its internal clock and this clock could be supplied to the other parts. Applying a common \SYNC pulse to all the ADCs will synchronize the conversion process on all the ADCs. Note that the modulator is not reset so there will always be an uncertainty of one modulator clock cycle between the different ADCs i.e. the conversions from the different ADCs may occur within one modulator clock cycle of each other.
Holding the \SYNC pin high will not affect any operation on the ADC and leaving it open when unused will also not affect the operation because of its internal pull up resistor to DVDD.
10. Does DOUT/RDY become High-Z when /CS is high?
Yes, when /CS is high, the DOUT/RDY pin is in high impedance state. Therefore, the DOUT/RDY pin will not indicate the end of the conversion. To determine when a conversion is ready, the status register can be read periodically, the RDY bit indicating when a conversion is ready. Alternatively, /CS can be taken low periodically and the DOUT/RDY pin can be monitored.
11. DOUT/RDY is not working or never goes low. What should I do?
Upon power up, reset the part by applying a number of consecutive ones to the interface (32 for AD779x, AD7780/81, AD7788/89/90/91, AD7170/71, 40 for AD719x, 64 for AD717x and AD7124). This will ensure that all registers are set to their default values. Take note that when /CS is taken high, the DOUT/ RDY pin is tri-stated. Therefore, the DOUT/RDY pin will not indicate the end of the conversion. So with /CS low, monitor the DOUT/RDY pin to see if the pin is pulsing at the default output data rate. Then try to change the output data rate by writing to the appropriate register. Read back the register to ensure that the correct value was written. Again, with /CS low, check that the DOUT/RDY pin is pulsing at the new selected output data rate.
When DOUT/RDY stops pulsing at any time and it stays high or low (even though the ADC is configured for continuous conversion mode), this indicates that the serial interface has become asynchronous (incorrect number of SCLK pulses, glitches on the SCLK line). Ensure that the correct number of SCLK pulses are being used for each read/write operation. It is also recommended to tie DIN and SCLK high when they are not being used to prevent glitches affecting the SPI interface.
12. Data available on DOUT is invalid or is not updating. What is wrong?
The data register is updated each time a conversion is complete and the DOUT/RDY pin goes low when a valid conversion is available. It is recommended to perform a reset after power up to ensure that all the registers are at their default values. You can then configure the part by writing to the registers. Try to read back the registers to ensure that the correct register values were written to the part. Conversions should be read by monitoring the DOUT/RDY pin. When the DOUT/RDY pin goes low, you should read the data register. If the DOUT/RDY pin is not used to indicate the end of conversions, it is possible that reads of the data register are performed while the data register is being updated, resulting in an invalid conversion being read. When several channels are enabled, the ADC (AD719x, AD7124, AD717x) automatically sequences through the enabled channels, performing one conversion on each channel per loop. The part only has one data register so, the SCLK needs to be fast enough to ensure the current conversion is read before the next conversion is complete. If you commence reading the data register in continuous conversion mode, then the data register is not updated until the read operation is complete. Therefore, if you use a slow SCLK, you will miss conversions from channels.
13. Data output clamped to all zeros or 1s. Why?
This can occur if there is an invalid conversion. The status register includes an error bit which is set to indicate that the result written to the ADC data register has been set to 0xFFFFFF or 0x000000. Error sources are normally due to overvoltage/undervoltages on the analog inputs or an invalid reference.