I have a question about AD7468 SAR ADC.The AD7648 has a specification about fclk as followings. (tabel-4 of the datasheet)
Parameter Limit at TMIN,TMAX Unit Description fSCLK 3.4 MHz max Mark/space ratio for the SCLK input is 40/60 to 60/40. 10 kHz min 1.6 V ≤ VDD ≤ 3 V; minimum fSCLK at which specifications are guaranteed. 20 kHz min VDD = 3.3 V; minimum fSCLK at which specifications are guaranteed. 150 kHz min VDD = 3.6 V; minimum fSCLK at which specifications are guaranteed.
It means that fclk has a limitation of lowest speed, affected by VDD.
Q1. Which performance will be affected if the fclk more slower than this ? SNR ? INL ? DNL ?
Q2. Would you tell the lowest frequency of fclk when the VDD is 3.4V ?
You are correct. The FSCLK minimum speed specification is determined by VDD. Unfortunately no performance specifications can be guaranteed while operating outside of this minimum specification, and you may see some deterioration in both AC and DC performance (this includes SNR, INL, DNL etc.).
As the datasheet does not define a specific FSCLK min for 3.4V you would have to use the FSCLK min specification defined for 3.6V (150 KHz) in order to guarantee specified performance.