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AD760x RESET glitches

Hi,

there are reports of AD760x devices suddenly returning only zeros due to glitches on the RESET line, like here or here, the latter unfortunately solved through a private message. We seem to have a similar problem.

Are there any solutions available except for performing a reset before each conversion?

Regards,

rehfi

  • HI,

       I am checking this and get back to you soon.

    Regards,

    Jonathan

  • Hi Rehfi,

       As of now, we recommend to perform a valid reset before each conversion while still looking possible cause.

    Regards,

    Jonathan 

  • Hi Jonathan,

    when we would do a new hardware design, what would you recommend to make the RESET input more robust?

    Regards,

    rehfi

  • Hi Jonathan,

    is this issue activly persued?

    Regards,
    rehfi

  • Hi Rehfi,

       I am working on this in the lab, performing some experiments, on how long would a glitch not to be considered as reset. I'll be discussing with the team. I'll feedback to you with the results of the discussion.

    Regards,

    Jonathan

  • Please do not mark this thread as "Assumed Answered" when my questions are still open. If this happens automatically, I could flood the forum with "Are we there yet?" to avoid that, but that won't help anybody.

    To give you an impression of my situation: We have several products out in the field, some of them are showing the behavior described above. And we are planning new products with the AD760x devices.

    For the devices in the field we can not do much more than applying workarounds, though there are applications were it is simply not possible to apply a reset before every conversion, i.e. due to latency reasons. And we have to tell the costumer why he has to do all this resets (yes, he want's to know that!)

    For new products I would need a solution, not only a workaround. When there isn't a solution available, then just say so, so we can put the devices onto out internal "not recommended for new designs" list.

    It's OK for me when a thorough answer takes some time, but i don't like to be put off.

    Regards,

    rehfi

  • Hi Rehfi,

       I did some evaluation and it would take around 40ns (specified at 50ns) pulse signal to reset the AD7606. A glitch at this long would be miss interpreted as a reset. What I can recommend for now is to add some capacitance on the reset line to limit the glitch. I will share this with my colleague and there are ways for a possible protection circuit. By the way, what type of application you are using the AD7606? I would like to know so I can have idea where it is expose to.

    Regards,

    Jonathan

  • Hi Jonathan,

    We are using the AD7609 on multiple data acquisition boards, with 2 to 4 devices doing simultaneous sampling. The board where we actually saw the problem is an isolated variant, with a Si8455 digital isolator driving the RESET line. The customer uses this board in a industrial PC for a hardware simulation application, but I don't know if it is used in a EMI susceptible environment.

    What about that 10.7 ns critical timing mentioned here?

    jcolao wrote:

    I will share this with my colleague and there are ways for a possible protection circuit.

    I would like to learn more about it...

    Regards,

    rehfi

  • Hi Rehfi,

       Is it okay for you to share the schematic of your application this for us to better understand the problem.

    Regards,

    Jonathan

  • Hi Jonathan,

    My application is like this:

    [FPGA] <--> [Isolation] <--> [AD7609]

    Isolation is done with Si8442 & Si8455.

    REF_SELECT, PSR#/SEL and STBY are pulled to VDRIVE, all other signal are actively driven, without pull-ups or pull-downs. The analog part corresponds to the AD7609 Eval Board schematics.

    Regards,

    rehfi