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AD7171: data conversion never ready


I'm incorporating AD7171 on a new board. I've so far assembled two of these with same result:

My problem is that the DOUT/RDY-pin never goes low after reset/power up. This is what I do:

 * Configure pins on the microcontroller (PDRST and SCLK as outputs on the microcontroller, DOUT/RDY as input)

 * Perform a reset: set PDRST hi for 300 ms, low for 300 ms, and hi again for 300 ms

 * Wait for DOUT/RDY to go low

But DOUT/RDY stays high no matter what.

If I leave the AD7171 in reset mode (PDRST lo) the DOUT/RDY goes into tristate as expected, causing the wait for DOUT/RDY to finish and garbage bits to be read. This makes me believe that the chip is not dead at least.

I'm currently bitbanging very slowly to be sure what happens. The microcontroller is an Atmel ATmega328P. Here's the code I'm using:

#define AD7171_RDY (PINB & (1 << 4))
#define AD7171_SCLK_LO PORTB &= ~(1 << 5)
#define AD7171_SCLK_HI PORTB |= (1 << 5);
#define AD7171_PDRST_LO PORTC &= ~(1 << 3)
#define AD7171_PDRST_HI PORTC |= 1 << 3

void ad7171_init()
    uint8_t i;
    uart0_send_string("ad7171 init\n");

    // !PDRST on PC3
    DDRC |= 1 << 3;

    // DOUT/!RDY on PB4
    // SCLK on PB5
    DDRB &= ~(1 << 4);
    DDRB |= 1 << 5;

    uart0_send_string("toggle reset\n");

    uart0_send_string("await rdy\n");
    while (AD7171_RDY) {


    for (i = 0; i < 24; i++) {
        if (AD7171_RDY) {
        } else {

    goto again;

I'll gladly post any additional info...

  • The code looks right to me as long as the delay works as it should. Is it possible to see the schematic from the micro to the AD7171. 

  • Here's the schematic:

    And here's the layout:

    I've only included the parts I think are relevant for this problem.

    Apart from the AD7171 there's also a MRF24J40MA and an ISP-header connected to the SPI signals. But I have one board with MRF24J40MA mounted, and one without, and both have the same error. The ISP is used to upload software to the MCU, but I've tried both with it in place and removed with no difference.

  • I would add a series resistor for the data lines. 100 ohms should be ok.  Adding a 10k pull-up resistor for the reset will ensure a known startup state. Also, I would recommend connecting Vref- to GND. If you are planning to only do single ended measurements connect AIN- to GND.

    That being said, these should not give your behavior. 

    Can I get a scope shot of the reset line, sclk, and DOUT/RDY when you power up and when the micro asserts and de-asserts the reset?

  • Hi, thanks for your suggestions! I fired up the scope and took some shots, but then I found my problem:

    It seems that DOUT/RDY will never indicate data ready when SCLK is low. This is not super obvious in the data sheet, but when I initialize SCLK to high state it started ticking. I get good measurements now with high precision. My only problem now is that every once in a while I get data 0xFFFF and status bits 0xFF. It's not hard to filter these conversions though so it's not a big problem.

    Thanks for your help!

  • Hi,

    We have generated an FAQ for digital communication issues on sigma delta ADCs. You can view it here Digital Interface FAQ - Sigma Delta ADC. You might find here a similar problem and how you may able to solve it. Hope this helps.