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AD7712 Output Data are always low


This is about receiving data register contents from AD7712.

First of all, I am using an Automatic Test Equipement to evaluate the AD7712. The ATE acts as a microcontroller to drive and read data from the ADC.  From the ATE we have also the supply voltages (AVdd and DVdd).

Master Clock is supply by an external fonction generator ( Square 10 MHz - CMOS Level )

The problem is that AD7712 cannot output Data. The outputs from the Data Reqister are always low.

I respect the latency  and the time for the output data rate

I follow the the Figure 13a on page 22 of the specification REV. F for the timing for reading operation from the data register

I would like my system to read data register continuously.

1. Power on

2 Activation of external MCLK

3. write control register (to enable 24-bit reading)

4. read control register (to check if control reg is written correctly)

5 Send differential voltage to AIN1

6 read data register with the ATE


+2.5V on ref in+

GND on ref in-

external clocking at 10.00MHz  CMOS Level (to MCLK IN)

UNIpolar input on AIN1 AIN2 unused

mode to gnd

standby to +5V

control register setting:

operating mode = normal, MD2=0, MD1=0, MD0=0

pga gain = 1, G2=0, G1=0, G0=0

channel selection = AIN1 low-level input, CH=0

power-down = normal,PD=0

word-length = 24-bit, WL=1

reserved = 1

burnout current = off, BO=0

bipolar/unipolar selection = bipolar, B/U = 1

filter selection, FS11-FS0, 12-bit, d1920

Thanks for your help

  • Hi,

    May I know what are your supply voltages as well as your input voltages? How is your SYNC pin connected? Normally when the result written to the ADC data register has been set to 0xFFFFFF or 0x000000 it indicates that there is an invalid conversion. Error sources are normally due to overvoltage/undervoltages on the analog inputs or an invalid reference. Can you check on this?



  • Hi Jellenie

    The ADC is supply with AVdd=DVdd=5.0   The internal Reference voltage is used to REFIN(+) and Vbias.  VSS=GND

    We used the Fully Differential Amplifier ADC Driver AD8476 to drive the differential channel AIN1 of the AD7712.

    The common mode voltage is at Vref/2 means that when we have 0v, Ain1(+)=Ain1(-)=1,25V and when we have 2.5V, Ain1(+)=Vref and Ain1(-)=0V

    When a new analog step voltage is set, SYNC pin is LOW, and goes HIGH to start the conversion process.  The analog voltage stay during all the process.


    For this test the analog voltage set to 2V means Ain1(+)=2,25 and Ain1(-)=0,250V

  • Hi Jellenie,

    I have just changing de analog input voltage to 800mV,

    and after SYNC High and wait 3 cycle of conversion, I have data from the Data Register. Then a data is available each cycle of output data Rate.

    But Five cycles after, the Output from the Data Register is always low. After every Read operation, DRDY_ toggle to high then LOW.

    And the results are not conformed to the expected. The value is closed to 1494111 ( 220mV )

    Thanks for your help.



  • Hi,

    Is it always 5 cycles after? One probable cause is that the digital interface is entering an unexpected state or lose synchronization. Can you monitor the DRDY pin if it is still pulsing beyond 5 cycles that you have mentioned? When DRDY stops pulsing at any time and it stays high this indicates that the serial interface has become asynchronous(incorrect number of SCLK pulses, glitches on the SCLK line). Data can be accessed only when DRDY is low and when it is high, no data transfer will take place. Ensure that the correct number of SCLK pulses are being used for each read/write operation. Can you also ensure that the SYNC is brought high at the correct time? When this pin is taken low, the modulator and filter are held in a reset state and the ADC is not converting.



  • Hi 

    I have just fixed the problem of level for the differential channel. It's an inversion of level for channel between input + and input +

    AIN(+) = 0.224v

    AIN1(-) = 2,224V

    After correction the result is conformed to the expected for 2Vdiff.

    But the problem of cycles with output of data register always low, as explained above, still there.


  • Hi,

    Sorry my explainations was not very clear.

    Number of SCLK is correct for each read operation.

    DRDY_ move to High after 24 SCLK then goes Low when a data is available.

    I have checked the number of wait state before read to be sure than I am not too fast versus the output data rate. FS11 to FS0, 12-bit, d1920 means output data rate : 10,17Hz.

    Frequency for SCLK: 200kHz

    But after five cycles of reads, the first bits, in the word, are correct but the remainder are low. And for the next cycles, all bits are low and stay until the end of the pattern.



  • Hi,

    Do you have an idea to fix this?



  • Hi,

    Sorry this was missed. May I know if you have solved the issue? I would like to see the scope shot of your digital interface if you could provide it that would be great. I was thinking if you have any timeout in your controller that may cause the issue? Can you monitor the actual input voltage and reference at the time you have an invalid conversions? We have to figure out what causes the issue. It's weird that you are getting a valid results then suddenly gone after 5cycles. When you reset the ADC and interface every after 5cycles, do you still get the same issue?



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