hi every one,
I have problem to run AD7091R-8, I use fpga to use this ADC but when I initialize the ADC and set the registers and then I want to read back the registers to verify them. but there is no signal in SDO pin, I think maybe the IC didn't receive my command correctly I changed my code to send no command just do a convert and then as it mentioned in the datasheet after get low the CS the IC will send converted data on the SDO automatically, but there is no signal on SDO pin yet. I will say the specification that I used to drive this IC please check it and help me to solve my problem.
*I send the data on the falling edge of the SCLK which the IC can receive it on the rising edge of the SCLK. is it right? IC will recieve data on the rising edge of the SCLK?
*as it mentioned in the datasheet the first data which is MSB bit will send out on the falling edge of CS and fpga will recive it on the first rising edge and the other bits will be send on the falling edge of SCLK and the fpga will receive them on the rising edge of the SCLK. is it right?
*I try hardware initialization and also software initialization but none of them have solved my problem.
I attached the signals in the first picture I use software reset and as you see there is no signal on SDO and in the second picture I use hardware reset and as you see again there is no signal on the SDO pin.
Could you please provide a scope shot of your hardware reset? The hardware reset action is the recommended reset action for the AD7091R-8. The software reset is only recommended for users that…
I believe you have found an error in the text of the data sheet. The timing diagram you reference is correct. Data on SDI should be written on the rising edge of SCLK. ADD4 should be written…
The state of SDO is controlled by the CS signal. Bringing CS low automatically drives SDO low and enables the SDO line. The convst signal has no influence over SDO. It is just used to initiate…
The state of SDO is controlled by the CS signal. Bringing CS low automatically drives SDO low and enables the SDO line. The convst signal has no influence over SDO. It is just used to initiate the conversion process.
The interface is always listening for a read or write command. A read or write transaction occurs when CS is brought low. The device expects to receive 16 serial clocks. To move to a new register address, the device must see a pulse on CS to signal that a new register address is about to be received. If the address pointer does not need to be updated (for example, when reading conversion results), data is not required to be written on SDI.
I was able to acquire an AD7091R-8 customer evaluation kit. I went into our lab and took some screen shots on the digital operation for comparison.
First, here is a data transfer on SDO. The device is reading a result on channel 0:
Blue --> CONVST
Magenta --> SDI
Blue --> SCLK
Green --> SDO
Next is a screen shot of the write transaction for changing a the enabled channels. I believe I enabled channels 0 and 5. You can see that the address is 0x1 and that the write bit has been set. Just remember, there is a one cycle delay for this write command to take effect.
I have also provided a screen shot of the read event. Remember, this is just the data. There is a one cycle delay relative to when the command is recognized for the device to produce the result. The command was written on the previous cycle This was a read of the channel register. I had enabled channels 0 and 4 here. For further info, see figure 52 in the data sheet.
The serial clock utilized was 60 MHz, so 20 MHz should be perfectly fine. Are you using the internal reference? When a reset occurs, the internal reference must be re-enabled.
I think in your image that you are reading correctly that 6 channels are enabled. However, I don't think you waited the correct one cycle delay.