AD7091R-8 problem

hi every one,

I have problem to run AD7091R-8, I use fpga to use this ADC but when I initialize the ADC and set the registers and then I want to read back the registers to verify them. but there is no signal in SDO pin, I think maybe the IC didn't receive my command correctly I changed my code to send no command just do a convert and  then as it mentioned in the datasheet after get low the CS the IC will send converted data on the SDO automatically, but there is no signal on SDO pin yet. I will say the specification that I used to drive this IC please check it and help me to solve my problem.

*SCLK: 20MHz

*I send the data on the falling edge of the SCLK which the IC can receive it on the rising edge of the SCLK. is it right? IC will recieve data on the rising edge of the SCLK?

*as it mentioned in the datasheet the first data which is MSB bit will send out on the falling edge of CS and fpga will recive it on the first rising edge and the other bits will be send on the falling edge of SCLK and the fpga will receive them on the rising edge of the SCLK. is it right?

*I try hardware initialization and also software initialization  but none of them have solved my problem.

I attached the signals in the first picture I use software reset and as you see there is no signal on SDO and in the second picture I use hardware reset and as you see again there is no signal on the SDO pin.

thanks

Matin

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  • 0
    •  Analog Employees 
    on Aug 29, 2017 5:51 PM

    Hi Matin,

    I believe you have found an error in the text of the data sheet.  The timing diagram you reference is correct.  Data on SDI should be written on the rising edge of SCLK.  ADD4 should be written on the first rising edge after an EOC occurs.  We will work to update the data sheet to convey rising edge operation.  The data on SDO can be read on either the rising or falling edge of SCLK as long as the setup and hold times in the timing spec table are adhered.

    When reading back register data, make sure that the RW bit is set to 0.  A 1 is used when writing.  A 0 is used when reading.

    -- Ryan

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  • 0
    •  Analog Employees 
    on Aug 29, 2017 5:51 PM

    Hi Matin,

    I believe you have found an error in the text of the data sheet.  The timing diagram you reference is correct.  Data on SDI should be written on the rising edge of SCLK.  ADD4 should be written on the first rising edge after an EOC occurs.  We will work to update the data sheet to convey rising edge operation.  The data on SDO can be read on either the rising or falling edge of SCLK as long as the setup and hold times in the timing spec table are adhered.

    When reading back register data, make sure that the RW bit is set to 0.  A 1 is used when writing.  A 0 is used when reading.

    -- Ryan

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