AD7091R-8 problem

hi every one,

I have problem to run AD7091R-8, I use fpga to use this ADC but when I initialize the ADC and set the registers and then I want to read back the registers to verify them. but there is no signal in SDO pin, I think maybe the IC didn't receive my command correctly I changed my code to send no command just do a convert and  then as it mentioned in the datasheet after get low the CS the IC will send converted data on the SDO automatically, but there is no signal on SDO pin yet. I will say the specification that I used to drive this IC please check it and help me to solve my problem.

*SCLK: 20MHz

*I send the data on the falling edge of the SCLK which the IC can receive it on the rising edge of the SCLK. is it right? IC will recieve data on the rising edge of the SCLK?

*as it mentioned in the datasheet the first data which is MSB bit will send out on the falling edge of CS and fpga will recive it on the first rising edge and the other bits will be send on the falling edge of SCLK and the fpga will receive them on the rising edge of the SCLK. is it right?

*I try hardware initialization and also software initialization  but none of them have solved my problem.

I attached the signals in the first picture I use software reset and as you see there is no signal on SDO and in the second picture I use hardware reset and as you see again there is no signal on the SDO pin.

thanks

Matin

attachments.zip
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  • 0
    •  Analog Employees 
    on Aug 25, 2017 1:19 AM

    Hi Matin,

    Could you please provide a scope shot of your hardware reset?  The hardware reset action is the recommended reset action for the AD7091R-8.  The software reset is only recommended for users that are pin limited and cannot dedicate a digital resource to the reset signal.

    After the device is powered up and a reset is applied, what configuration settings are you writing to registers 0x01 and 0x02?

    You are correct that a falling edge on SCLK results in data being shifted onto SDO.  The rising edge of SCLK is used for writing configuration data to the ADC.  SDO results can be read on either the rising edge or falling edge of SCLK assuming the proper setup time has been provided.

    -- Ryan

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  • 0
    •  Analog Employees 
    on Aug 25, 2017 1:19 AM

    Hi Matin,

    Could you please provide a scope shot of your hardware reset?  The hardware reset action is the recommended reset action for the AD7091R-8.  The software reset is only recommended for users that are pin limited and cannot dedicate a digital resource to the reset signal.

    After the device is powered up and a reset is applied, what configuration settings are you writing to registers 0x01 and 0x02?

    You are correct that a falling edge on SCLK results in data being shifted onto SDO.  The rising edge of SCLK is used for writing configuration data to the ADC.  SDO results can be read on either the rising edge or falling edge of SCLK assuming the proper setup time has been provided.

    -- Ryan

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