AD7091R-8 problem

hi every one,

I have problem to run AD7091R-8, I use fpga to use this ADC but when I initialize the ADC and set the registers and then I want to read back the registers to verify them. but there is no signal in SDO pin, I think maybe the IC didn't receive my command correctly I changed my code to send no command just do a convert and  then as it mentioned in the datasheet after get low the CS the IC will send converted data on the SDO automatically, but there is no signal on SDO pin yet. I will say the specification that I used to drive this IC please check it and help me to solve my problem.

*SCLK: 20MHz

*I send the data on the falling edge of the SCLK which the IC can receive it on the rising edge of the SCLK. is it right? IC will recieve data on the rising edge of the SCLK?

*as it mentioned in the datasheet the first data which is MSB bit will send out on the falling edge of CS and fpga will recive it on the first rising edge and the other bits will be send on the falling edge of SCLK and the fpga will receive them on the rising edge of the SCLK. is it right?

*I try hardware initialization and also software initialization  but none of them have solved my problem.

I attached the signals in the first picture I use software reset and as you see there is no signal on SDO and in the second picture I use hardware reset and as you see again there is no signal on the SDO pin.


  • 0
    •  Analog Employees 
    on Aug 25, 2017 1:19 AM

    Hi Matin,

    Could you please provide a scope shot of your hardware reset?  The hardware reset action is the recommended reset action for the AD7091R-8.  The software reset is only recommended for users that are pin limited and cannot dedicate a digital resource to the reset signal.

    After the device is powered up and a reset is applied, what configuration settings are you writing to registers 0x01 and 0x02?

    You are correct that a falling edge on SCLK results in data being shifted onto SDO.  The rising edge of SCLK is used for writing configuration data to the ADC.  SDO results can be read on either the rising edge or falling edge of SCLK assuming the proper setup time has been provided.

    -- Ryan

  • dear Ryian,

    I have sent scope shot of my hardware reset but I attach it again. as you see the pulse width is 25 ns.

    I write "0000110000111111" to 0X01 register as I use just 6 channel of the ADC and I write "0001010001111000"to 0X02 register.

    I have one more question, in the datasheet on the page 12 it says "Data is clocked into the registers on the falling edge of the SCLK input. Provide data MSB first." but on the timing diagram it draw the tSSDISCLK and tHSDISCLK arrows towards the rising edge of SCLK as I attached the diagram. so I can't understand that the IC receive data on the rising edge or on the falling edge! could you please tell me the correct answer?



  • 0
    •  Analog Employees 
    on Aug 29, 2017 5:51 PM

    Hi Matin,

    I believe you have found an error in the text of the data sheet.  The timing diagram you reference is correct.  Data on SDI should be written on the rising edge of SCLK.  ADD4 should be written on the first rising edge after an EOC occurs.  We will work to update the data sheet to convey rising edge operation.  The data on SDO can be read on either the rising or falling edge of SCLK as long as the setup and hold times in the timing spec table are adhered.

    When reading back register data, make sure that the RW bit is set to 0.  A 1 is used when writing.  A 0 is used when reading.

    -- Ryan

  • Hi every one,

    I want to use a AD7091R-8 via FPGA and I have used vhdl code to do it, in this code which is describing below I want to test the SPI of the ADC, so I just send a 16bit data to write to channel register and then I send another 16bit data to read the same register but the data which is sent by AD7091R-8 is not correct.

    at first there was no signal in sdo pin of ad7091R-8 because of hardware problem I fixed it but now I have some signal on sdo but it is not correct.

    in the picture below you can see chip scope analyzer which I test my fpga board with it, as you see at first there is a 25 ns pulse on the reset pin of fpga after 250 ns sclk start to clocked out and also cs get low, when cs get low fpga starts to send signal on falling edge of sclk which ADC can receive it on the rising edge of SCLK and it also sends MSB first. I want to send "0000110000111111" as you see it is the channel register which its address is 0X01 and 11th bit set to '1' which is meaning it is a write command. after sending these 16 bit, cs get high and after a while it gets low again to send a read command, read register is"0000100000000000" which is a 16 bit register and it is obvious that the address of the register is 0X01 and the 11th is set to '0' to do a read command, after sending all 16 bit cs get high and after a while it get low which it is ADC's turn to send data but the data is totally incorrect! now I have some question

    1- in this code i just wanted to test SPI and all the time, convst was high so sdo should be high impedance all the time before read command sent but as you see at the first time that cs get low, sdi change to low! why?

    2-why I did not recieve correct data? 

    sclk is 20MHz


  • 0
    •  Analog Employees 
    on Sep 5, 2017 10:31 PM

    Hi Matin,

    The state of SDO is controlled by the CS signal.  Bringing CS low automatically drives SDO low and enables the SDO line.  The convst signal has no influence over SDO.  It is just used to initiate the conversion process.

    The interface is always listening for a read or write command.  A read or write transaction occurs when CS is brought low.  The device expects to receive 16 serial clocks.  To move to a new register address, the device must see a pulse on CS to signal that a new register address is about to be received.  If the address pointer does not need to be updated (for example, when reading conversion results), data is not required to be written on SDI. 

    I was able to acquire an AD7091R-8 customer evaluation kit.  I went into our lab and took some screen shots on the digital operation for comparison.

    First, here is a data transfer on SDO.  The device is reading a result on channel 0:

    Blue --> CONVST

    Magenta --> SDI

    Blue --> SCLK

    Green --> SDO

    Next is a screen shot of the write transaction for changing a the enabled channels.  I believe I enabled channels 0 and 5.  You can see that the address is 0x1 and that the write bit has been set.  Just remember, there is a one cycle delay for this write command to take effect.

    I have also provided a screen shot of the read event.  Remember, this is just the data.  There is a one cycle delay relative to when the command is recognized for the device to produce the result. The command was written on the previous cycle  This was a read of the channel register.  I had enabled channels 0 and 4 here. For further info, see figure 52 in the data sheet.

    The serial clock utilized was 60 MHz, so 20 MHz should be perfectly fine.  Are you using the internal reference?  When a reset occurs, the internal reference must be re-enabled.

    I think in your image that you are reading correctly that 6 channels are enabled.  However, I don't think you waited the correct one cycle delay.

    -- Ryan