SPI Communication Issue with AD7264

Question

Good morning. 
 We are using AD7264 in our design. 
 AD7264 is interfaced with iMX6 NXP Processor. 
 We would be grateful to have any insight on the queries detailed. 
 Scenario: 
 Validating SPI Communication with AD7264 
 Queries 
 
 Is there a specific initialisation sequence for AD7264? 
 Does there exist a reference code for initialisation? 
 Can internal registers be read from / written to without doing any calibration? 
 Data is transferred to AD7264 in a packet of 8 bits. An idle period of 4.5 uSec is observed between two byte transfers. Will it affect SPI communication? (Please refer image AD7264_SCLK_TimeDelay.BMP ) 
 Is there a max. time delay acceptable between transfer of successive bytes? 
 How critical are DIN setup time (3 nSec min.) and DIN hold time (3 nSec min.)? In our case, setup time is 0 and hold time is one SCLK cycle. 
 
 Steps carried out & observations: 
 
 Read contents of ADC A Internal Offset Register after power-on. (All "0" as suggested in datasheet Page # 23) 
 WRITE a known value (NOT CALIBRATION VALUE). 
 Read contents of ADC A Internal Offset Register. All "0". Expected is the written known value. 
 Carry-out (1) to (3) for
 
 ADC B Internal Offset Register 
 ADC A External Gain Register 
 ADC B External Gain Register Results are the same as in case of ADC A Internal Offset Register.

Checks Performed

Checks Performed 
 Observations

Chip select polarity 
 Idle high Active low during transmission

SCLK polarity 
 Idle high Active low during transmission

Chip select to SCLK setup time 
 12 uSec Required is 10 nSec min. (Datasheet Page # 29)

SCLK frequency 
 1 MHz

MOSI Data stream on AD7264 PD0/DIN pin 
 Expected data stream as per the WRITE / READ scenarios

MOSI data transfer w.r.t SCLK 
 Bits are transferred on "falling edge" of SCLK

AVcc 
 5 V

Vdrive 
 5 V

Vref 
 2.5 external

Bit Streams used

Requirement 
 Bit stream

ADC A Internal Offset Reg. Read 
 (MSB) 0001 0010 0001 0001 0000 0000 0000 0000 (LSB) Last 20 LSBs are to generate SCLK for data receiving

ADC A Internal Offset Reg. Write 
 (MSB) 0010 0101 0101 0101 0000 (LSB) b15-b4 : dummy data 0x55 to validate read operation

Best regards, 
 -- Utpal

jcolao · Accepted Answer

Hi UtpalT, 
 Please see responses below.

Is there a specific initialisation sequence for AD7264? To power up the AD7264 you can refer to the power up condition section of the datasheet (Page 22). The AD7264 can be powered up through pin driven mode or control register mode. When applying power to the AD7264, please refer to the abs max rating. Make sure that, when powering up the supply values are followed. For example on tale 3, The AVcc should be applied first before the Vdrive and VrefA and VrefB. 
 Does there exist a reference code for initialisation? The available code that I can refer to is in the wiki page of AD7262 (co family of AD7264). 
 Can internal registers be read from / written to without doing any calibration? Register data can be read or write to without performing calibration. But to have an accurate measurement by removing offset and gain errors, I recommend to do calibration. 
 Data is transferred to AD7264 in a packet of 8 bits. An idle period of 4.5 uSec is observed between two byte transfers. Will it affect SPI communication? (Please refer image AD7264_SCLK_TimeDelay.BMP ) Can you please give details on what you are trying to do here. 
 Is there a max. time delay acceptable between transfer of successive bytes? Can you please give details on what you are trying to do here. 
 How critical are DIN setup time (3 nSec min.) and DIN hold time (3 nSec min.)? In our case, setup time is 0 and hold time is one SCLK cycle. The DIN set up time and DIN hold time is critical because this help you set up the time that the microcontroller will read the data. To make sure that data bits is read correctly, need to consider these times. 
 
 Regards, 
 Jonathan)

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SPI Communication Issue with AD7264