AD 7822 Confusing ~PD and ~CONVST

Question

Good day everyone! 
 I'm about to use AD 7822 but as I read the datasheet, I got confused regarding the ~PD and ~CONVST. The AD 7822 powers up (getting ready) if ~PD is logic high OR ~CONVST is logic high (after #ns of ~EOC duration). The word OR here confuses me. 
 1) If I tied ~PD permanently high to Vcc, does that mean the AD 7822 will not power down at all even if after ~EOC, ~CONVST is low? Is the state of ~CONVST ignored regarding power down if ~PD is always high? 
 2) Does that mean that a 1µs power up time will always be needed before every conversion start even if ~PD is tied to Vcc? 
 3) Can I use a continuous crystal oscillator (50/50) for ~CONVST, or does ~CONVST just accepts pulses or "per request" conversion? If yes, does that mean frequency of ~CONVST and sampling frequency is equal? 
 I've wanted to use 7822 with a continuous crystal oscillator for clock (50% duty cycle) and I am trying to compute for the frequency to achieve a little more than 1.5MSPS (my signal is 750kHz). I need a continuous ADC and the 1µs power up time (if it powered down during the signal) will mean that AD 7822 is not for the job. 
 Thank you very much. 
 ps. I will use ad 7822 with arduino.

jcolao · Accepted Answer

Hi Mike3886, 
 Figuring the set up, this may work, but please take note at 560ns period for the CONSVT, there will be exactly 30ns between the RD rising edge and the next CONVST falling edge (T3), which is very tight. Please make sure that this timing is met always during the conversion. Some deviation may affect the conversion process. 
 Regards, 
 Jonathan)

jcolao · Answer

Hi Miek3886, 
 Please refer to response to each question below. 
 1) If I tied ~PD permanently high to Vcc, does that mean the AD 7822 will not power down at all even if after ~EOC, ~CONVST is low? Is the state of ~CONVST ignored regarding power down if ~PD is always high? 
 The AD7822 can still enter power down with PD always high. The AD7822 can enter mode 2, automatic power down at the end of conversion. You can refer to figure 25 of the datasheet. 
 
 2) Does that mean that a 1µs power up time will always be needed before every conversion start even if ~PD is tied to 
 Vcc? power up time is not needed every conversion. Power up time is needed during when VDD is first connected and when it has been from a power down (like mode 2). 
 3) Can I use a continuous crystal oscillator (50/50) for ~CONVST, or does ~CONVST just accepts pulses or "per request" conversion? If yes, does that mean frequency of ~CONVST and sampling frequency is equal? 
 I am not sure on how would you do it. But if you are going to use crystal oscillator at 50% duty cycle that means high time and low time are equal. Checking on the figure 24 and figure 25, there would be different high time and low time of the CONVST. The low time is much longer as it will consider the conversion time plus the reading of the data time. CONVST can accept pulses, but proper timing must be followed for conversion and reading of data. 
 Regards, 
 Jonathan