AD 7822 Confusing ~PD and ~CONVST

Good day everyone!

   I'm about to use AD 7822 but as I read the datasheet, I got confused regarding the ~PD and ~CONVST. The AD 7822 powers up (getting ready) if ~PD is logic high OR ~CONVST is logic high (after #ns of ~EOC duration). The word OR here confuses me.

1) If I tied ~PD permanently high to Vcc, does that mean the AD 7822 will not power down at all even if after ~EOC, ~CONVST is low? Is the state of ~CONVST ignored regarding power down if ~PD is always high?

2) Does that mean that a 1µs power up time will always be needed before every conversion start even if ~PD is tied to Vcc?

3) Can I use a continuous crystal oscillator (50/50) for ~CONVST, or does ~CONVST just accepts pulses or "per request" conversion? If yes, does that mean frequency of ~CONVST and sampling frequency is equal?

   I've wanted to use 7822 with a continuous crystal oscillator for clock (50% duty cycle) and I am trying to compute for the frequency to achieve a little more than 1.5MSPS (my signal is 750kHz). I need a continuous ADC and the 1µs power up time (if it powered down during the signal) will mean that AD 7822 is not for the job.

Thank you very much.


ps. I will use ad 7822 with arduino.

ad7822.pdf
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  • Thank you very much.

    Uhmm,could you please confirm if I am correct in this:

       After power up, /CONVST goes low and a conversion starts (420ns, t1 maximum), then /EOC will go low for 110ns (t4). 30ns (t3) is the minimum time between the rising edge of RD and the next falling edge of convert start. I tied /EOC, /RD, and /CS and thus a conversion and read is 560ns wide (from mode 2 explanation in page 16, and stand alone figure 31 page 19).
    If I am to use 50% duty cycle clock with period of also 560ns, then for the 2nd half of the period the /CONVST is high and the device will not power down after the /RD check (/RD tied to /EOC)? Then this means that if 560ns (if fixed) is the minimum time for a conversion and 1785714.286 is the maximum samples per second 7822 offers. Am I correct in this?

    <if given the minimum t1 of 330ns, then an 8-bit data every 470ns is available (2127659.574 throughput)>

    Thank you again. 

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  • Thank you very much.

    Uhmm,could you please confirm if I am correct in this:

       After power up, /CONVST goes low and a conversion starts (420ns, t1 maximum), then /EOC will go low for 110ns (t4). 30ns (t3) is the minimum time between the rising edge of RD and the next falling edge of convert start. I tied /EOC, /RD, and /CS and thus a conversion and read is 560ns wide (from mode 2 explanation in page 16, and stand alone figure 31 page 19).
    If I am to use 50% duty cycle clock with period of also 560ns, then for the 2nd half of the period the /CONVST is high and the device will not power down after the /RD check (/RD tied to /EOC)? Then this means that if 560ns (if fixed) is the minimum time for a conversion and 1785714.286 is the maximum samples per second 7822 offers. Am I correct in this?

    <if given the minimum t1 of 330ns, then an 8-bit data every 470ns is available (2127659.574 throughput)>

    Thank you again. 

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