AD 7822 Confusing ~PD and ~CONVST

Good day everyone!

   I'm about to use AD 7822 but as I read the datasheet, I got confused regarding the ~PD and ~CONVST. The AD 7822 powers up (getting ready) if ~PD is logic high OR ~CONVST is logic high (after #ns of ~EOC duration). The word OR here confuses me.

1) If I tied ~PD permanently high to Vcc, does that mean the AD 7822 will not power down at all even if after ~EOC, ~CONVST is low? Is the state of ~CONVST ignored regarding power down if ~PD is always high?

2) Does that mean that a 1µs power up time will always be needed before every conversion start even if ~PD is tied to Vcc?

3) Can I use a continuous crystal oscillator (50/50) for ~CONVST, or does ~CONVST just accepts pulses or "per request" conversion? If yes, does that mean frequency of ~CONVST and sampling frequency is equal?

   I've wanted to use 7822 with a continuous crystal oscillator for clock (50% duty cycle) and I am trying to compute for the frequency to achieve a little more than 1.5MSPS (my signal is 750kHz). I need a continuous ADC and the 1µs power up time (if it powered down during the signal) will mean that AD 7822 is not for the job.

Thank you very much.


ps. I will use ad 7822 with arduino.

ad7822.pdf
  • 0
    •  Analog Employees 
    on Sep 6, 2017 12:36 AM

    Hi Miek3886,

       Please refer to response to each question below.

       1) If I tied ~PD permanently high to Vcc, does that mean the AD 7822 will not power down at all even if after ~EOC, ~CONVST is low? Is the state of ~CONVST ignored regarding power down if ~PD is always high?

       The AD7822 can still enter power down with PD always high. The AD7822 can enter mode 2, automatic power down at the end of conversion. You can refer to figure 25 of the datasheet.

      

      2) Does that mean that a 1µs power up time will always be needed before every conversion start even if ~PD is tied to  

      Vcc? power up time is not needed every conversion. Power up time is needed during when VDD is first connected and    when it has been from a power down (like mode 2).

    3) Can I use a continuous crystal oscillator (50/50) for ~CONVST, or does ~CONVST just accepts pulses or "per request" conversion? If yes, does that mean frequency of ~CONVST and sampling frequency is equal?

       I am not sure on how would you do it. But if you are going to use crystal oscillator at 50% duty cycle that means high time and low time are equal. Checking on the figure 24 and figure 25, there would be different high time and low time of the CONVST. The low time is much longer as it will consider the conversion time plus the reading of the data time. CONVST can accept pulses, but proper timing must be followed for conversion and reading of data.

    Regards,

    Jonathan

  • Thank you very much.

    Uhmm,could you please confirm if I am correct in this:

       After power up, /CONVST goes low and a conversion starts (420ns, t1 maximum), then /EOC will go low for 110ns (t4). 30ns (t3) is the minimum time between the rising edge of RD and the next falling edge of convert start. I tied /EOC, /RD, and /CS and thus a conversion and read is 560ns wide (from mode 2 explanation in page 16, and stand alone figure 31 page 19).
    If I am to use 50% duty cycle clock with period of also 560ns, then for the 2nd half of the period the /CONVST is high and the device will not power down after the /RD check (/RD tied to /EOC)? Then this means that if 560ns (if fixed) is the minimum time for a conversion and 1785714.286 is the maximum samples per second 7822 offers. Am I correct in this?

    <if given the minimum t1 of 330ns, then an 8-bit data every 470ns is available (2127659.574 throughput)>

    Thank you again. 

  • 0
    •  Analog Employees 
    on Sep 18, 2017 5:50 PM

    Hi Mike3886,

       Figuring the set up, this may work, but please take note at 560ns period for the CONSVT, there will be exactly  30ns between the RD rising edge and the next CONVST falling edge (T3), which is very tight. Please make sure that this timing is met always during the conversion. Some deviation may affect the conversion process.

    Regards,

    Jonathan

  • An out of the market 50% duty crystal standard frequency is 1.8432 MHz (period of 543 ns). I just hope that my 7822 will not max out that 420ns conversion time. Given the period of the crystal max conversion time should be 403 ns to have a continuous sampling.
    I can't find in the datasheet a parameter that affects conversion time.  I'm assuming temperature and analog voltage.

    Anyways, maraming salamat!