AD7761 Throughput and Dclk

Hi,

There are a number of factors to consider in order to calculate the minimum DCLK rate. The first point I would make is that MCLK does not have to be a fixed 32.768MHz. 32MHz is the MCLK needed to achieve the highest output data rate (ODR). Assuming you want the lowest power solution for daisy chaining 3 devices, assuming 2 DOUTs in use, I would calculate it as follows:

• Minimum DCLK needed is - 16,000 samples x 24 bits per conversion x 4 channels per DOUT x 3 devices = 4.608MHz minimum.
• Lowest MCLK possible is - 16kSPS x 32 (for decimation) x 32 (for internal clock divider, low power mode) = 16.384MHz.
• The DCLK divide option needed is DCLK/2 since DCLK/4 does not meet the 4.608MHz requirement.
• Fmod remains within the recommended rate of 0.036 to 1.024 MHz for low power mode.

The Pin Control settings would then be set as follows:

Dec1      0

Dec0      0

Mode3    0

Mode2    0

Mode1    0

Mode0    1

You also have the option to select either a sinc or wideband filter. If a higher performance configuration is needed this is also possible at the expense of burning more power by changing power modes. You could also use a 32.768MHz MCLK and decimate by 64 rather than 32 for greater performance

Regards

Niall