Bad data and resets when interfacing the AD7124 to Raspberry Pi

Summary:

I am trying to measure a 4 wire bridge load cell with a PGA gain of 128. I only seem to get valid data when I use low power mode, If I use medium or high power modes, the values do not change with cell loads and stay in the 7fffb0 to 8000ff range.  Is this a data output rate or filter problem?  If so, suggested values would be appreciated. (I started playing with post  filters and that sped up the conversion time but didn't fix the data output problem.)

A second problem is when I try to measure the temperature sensor or internal reference by connecting one to AINP and AINM to ground, a reset seems to occur as all the registers are set to their default values and the POR bit is set after the conversion is initiated.

I'm thinking a timing problem and have been playing with inserting delays between accessing the AD7124 but they don't help.  Now I'm wondering if the Pi is fast enough.

Thanks!

Gory Details:

I'm trying to develop code for the AD7124-8 using the EVAL-AD7124-8SDZ connected directly to the Raspberry Pi SPI pins:

Raspberry Pi Header                         EVAL-AD7124-8SDZ

19  GPIO 10 MOSI                              DIN

21  GPIO 09 MISO                              DOUT

23  GPIO 11 SCLK                              SCLK

24 GPIO 08 CE0                                 CE

06 Ground                                            Ground

I believe I am able to talk to the AD7124.  Everything works as expected, the ID register returns 14, the status register return 90 then the POR bit clears on the second read.  I set up Channel 1 to read AIN6 and AIN7 using setup 1 with a gain of 128. This is the output of a simple test program:

Sent 64 ones to reset
ID register: 14
Status register: 90
Status register: 80
09 Channel 0: 80 01 10000000 00000001
0A Channel 1: 90 c7 10010000 11000111
0B Channel 2: 00 01 00000000 00000001
0C Channel 3: 00 01 00000000 00000001
0D Channel 4: 00 01 00000000 00000001
0E Channel 5: 00 01 00000000 00000001
0F Channel 6: 00 01 00000000 00000001
10 Channel 7: 00 01 00000000 00000001
11 Channel 8: 00 01 00000000 00000001
12 Channel 9: 00 01 00000000 00000001
13 Channel 10: 00 01 00000000 00000001
14 Channel 11: 00 01 00000000 00000001
15 Channel 12: 00 01 00000000 00000001
16 Channel 13: 00 01 00000000 00000001
17 Channel 14: 00 01 00000000 00000001
18 Channel 15: 00 01 00000000 00000001
Number of active channels: 2
19 Config 0: 08 60 00001000 01100000
1A Config 1: 08 67 00001000 01100111
1B Config 2: 08 60 00001000 01100000
1C Config 3: 08 60 00001000 01100000
1D Config 4: 08 60 00001000 01100000
1E Config 5: 08 60 00001000 01100000
1F Config 6: 08 60 00001000 01100000
20 Config 7: 08 60 00001000 01100000
21 Filter 0: 06 01 80 00000110 00000001 10000000
22 Filter 1: FD 01 80 11111101 00000001 10000000
23 Filter 2: 06 01 80 00000110 00000001 10000000
24 Filter 3: 06 01 80 00000110 00000001 10000000
25 Filter 4: 06 01 80 00000110 00000001 10000000
26 Filter 5: 06 01 80 00000110 00000001 10000000
27 Filter 6: 06 01 80 00000110 00000001 10000000
28 Filter 7: 06 01 80 00000110 00000001 10000000
Beginning conversion
Timeout: 114
Data: 7fffb0 Status: 00
Timeout: 30
Data: 84f42c Status: 01
Timeout: 112
Data: 7fffb4 Status: 00
Timeout: 30
Data: 84f4d3 Status: 01
Timeout: 111
Data: 7fffb0 Status: 00

Timeout is the number of time it looped checking the Not Ready bit in the status register.  That loop has a minimum of a 1 msec wait  usleep(1000); each pass.

Parents
  • 0
    •  Analog Employees 
    on Nov 6, 2017 12:34 AM

    Hi,

    Yes, the AVDD should be 3.3V. The analog part will not power up if AVDD is below the minimum specified level of 2.7V(low and mid power mode) and 2.9V (full power mode). Can you check if all of the jumpers and connections are at all default connections as shown on the user guide? AVDD is 3.3V at default settings. If everything is at default setup, try to remove any link at SL7 and check again the output of ADP1720 (U7). This is just to check if the regulator is providing the correct output voltage of 3.3V. Try also to check if there are any other shorted connections on the board that should not be connected.

    Thanks,

    Jellenie 

Reply
  • 0
    •  Analog Employees 
    on Nov 6, 2017 12:34 AM

    Hi,

    Yes, the AVDD should be 3.3V. The analog part will not power up if AVDD is below the minimum specified level of 2.7V(low and mid power mode) and 2.9V (full power mode). Can you check if all of the jumpers and connections are at all default connections as shown on the user guide? AVDD is 3.3V at default settings. If everything is at default setup, try to remove any link at SL7 and check again the output of ADP1720 (U7). This is just to check if the regulator is providing the correct output voltage of 3.3V. Try also to check if there are any other shorted connections on the board that should not be connected.

    Thanks,

    Jellenie 

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