Bad data and resets when interfacing the AD7124 to Raspberry Pi

Summary:

I am trying to measure a 4 wire bridge load cell with a PGA gain of 128. I only seem to get valid data when I use low power mode, If I use medium or high power modes, the values do not change with cell loads and stay in the 7fffb0 to 8000ff range.  Is this a data output rate or filter problem?  If so, suggested values would be appreciated. (I started playing with post  filters and that sped up the conversion time but didn't fix the data output problem.)

A second problem is when I try to measure the temperature sensor or internal reference by connecting one to AINP and AINM to ground, a reset seems to occur as all the registers are set to their default values and the POR bit is set after the conversion is initiated.

I'm thinking a timing problem and have been playing with inserting delays between accessing the AD7124 but they don't help.  Now I'm wondering if the Pi is fast enough.

Thanks!

Gory Details:

I'm trying to develop code for the AD7124-8 using the EVAL-AD7124-8SDZ connected directly to the Raspberry Pi SPI pins:

Raspberry Pi Header                         EVAL-AD7124-8SDZ

19  GPIO 10 MOSI                              DIN

21  GPIO 09 MISO                              DOUT

23  GPIO 11 SCLK                              SCLK

24 GPIO 08 CE0                                 CE

06 Ground                                            Ground

I believe I am able to talk to the AD7124.  Everything works as expected, the ID register returns 14, the status register return 90 then the POR bit clears on the second read.  I set up Channel 1 to read AIN6 and AIN7 using setup 1 with a gain of 128. This is the output of a simple test program:

Sent 64 ones to reset
ID register: 14
Status register: 90
Status register: 80
09 Channel 0: 80 01 10000000 00000001
0A Channel 1: 90 c7 10010000 11000111
0B Channel 2: 00 01 00000000 00000001
0C Channel 3: 00 01 00000000 00000001
0D Channel 4: 00 01 00000000 00000001
0E Channel 5: 00 01 00000000 00000001
0F Channel 6: 00 01 00000000 00000001
10 Channel 7: 00 01 00000000 00000001
11 Channel 8: 00 01 00000000 00000001
12 Channel 9: 00 01 00000000 00000001
13 Channel 10: 00 01 00000000 00000001
14 Channel 11: 00 01 00000000 00000001
15 Channel 12: 00 01 00000000 00000001
16 Channel 13: 00 01 00000000 00000001
17 Channel 14: 00 01 00000000 00000001
18 Channel 15: 00 01 00000000 00000001
Number of active channels: 2
19 Config 0: 08 60 00001000 01100000
1A Config 1: 08 67 00001000 01100111
1B Config 2: 08 60 00001000 01100000
1C Config 3: 08 60 00001000 01100000
1D Config 4: 08 60 00001000 01100000
1E Config 5: 08 60 00001000 01100000
1F Config 6: 08 60 00001000 01100000
20 Config 7: 08 60 00001000 01100000
21 Filter 0: 06 01 80 00000110 00000001 10000000
22 Filter 1: FD 01 80 11111101 00000001 10000000
23 Filter 2: 06 01 80 00000110 00000001 10000000
24 Filter 3: 06 01 80 00000110 00000001 10000000
25 Filter 4: 06 01 80 00000110 00000001 10000000
26 Filter 5: 06 01 80 00000110 00000001 10000000
27 Filter 6: 06 01 80 00000110 00000001 10000000
28 Filter 7: 06 01 80 00000110 00000001 10000000
Beginning conversion
Timeout: 114
Data: 7fffb0 Status: 00
Timeout: 30
Data: 84f42c Status: 01
Timeout: 112
Data: 7fffb4 Status: 00
Timeout: 30
Data: 84f4d3 Status: 01
Timeout: 111
Data: 7fffb0 Status: 00

Timeout is the number of time it looped checking the Not Ready bit in the status register.  That loop has a minimum of a 1 msec wait  usleep(1000); each pass.

  • 0
    •  Analog Employees 
    on Oct 27, 2017 12:53 AM

    Hi,

    We'll look into this and get back to you. For the meantime, can you also send us your schematic and input settings?

    Thanks,

    Jellenie

  • Thank you.

    For schematics, please refer to EVAL-AD7124-8SDZ_UG-856.pdf

    I only have a Raspberry Pi (powered by a wall wart) connected to the EVAL-AD7124-8SDZ board (powered by the wall wart supplied with board) via ground, DIN, DOUT, SCLK, and CS (standard 4 wire SPI).  The EVAL-AD7124-8SDZ has all the jumpers in their default settings (ie I haven't touched them) except LK5 (Noise Test) on AIN0 and AIN1.

    I get the same results with or without any inputs connected to the EVAL-AD7124-8SDZ.

    I want to check this again and will update this if it changes, but it appears that AVdd is 1.9 VDC.  I was expecting closer to 3.3 as I thought this was running off a single ended supply.

    On figure 28 page 22, I'm reading about 1.9 VDC across C43.  I started checking AVdd because on Figure 26 page 20, there is an error on the wiring on J10/J11 it shows AVdd shorted to REFIN+   OH!  my mistake I see there is no connection dot there.  Any way, I'm reading 2.5 VDC on REFIN+ and 1.9 VDC on AVDD on J10/J11.

    I believe that the spec calls for a min of 2.7 AVdd to AVss

    For input settings, I'm assuming registers?  When I start my test program, after initialization. I read and dump the registers Since my first post, I have enabled some of the error conditions and print the error register on each ADC read.  I have also set the SPI clock freq much higher from the default of about 32KHz to around 3-6 MHz.  The timing loop delay is 100 microseconds (plus serial communication and overhead).  There are 4 data reads (two scans) after the register dump.

    unsigned int timeout=100000;
    char busy = 1;
    while( busy && timeout )
      {
      wrBuf[0]= 0x40;   
      bcm2835_spi_transfernb(wrBuf, rdBuf, 2);   /* Read the Status Register */
      busy = rdBuf[1] & 0x80 ;                                /* Test the Not Ready bit */
      usleep(100);                                                   /* wait 0.1 msec */
      timeout--;
      }

    Sent 64 ones to reset
    ID register: 14
    Status register: 90
    Status register: 80
    06 Error : 00 00 00 00000000 00000000 00000000
    07 Error Enab: 03 F0 38 00000011 11110000 00111000
    09 Channel 0: 80 e6 10000000 11100110
    0A Channel 1: 80 c7 10000000 11000111
    0B Channel 2: 00 01 00000000 00000001
    0C Channel 3: 00 01 00000000 00000001
    0D Channel 4: 00 01 00000000 00000001
    0E Channel 5: 00 01 00000000 00000001
    0F Channel 6: 00 01 00000000 00000001
    10 Channel 7: 00 01 00000000 00000001
    11 Channel 8: 00 01 00000000 00000001
    12 Channel 9: 00 01 00000000 00000001
    13 Channel 10: 00 01 00000000 00000001
    14 Channel 11: 00 01 00000000 00000001
    15 Channel 12: 00 01 00000000 00000001
    16 Channel 13: 00 01 00000000 00000001
    17 Channel 14: 00 01 00000000 00000001
    18 Channel 15: 00 01 00000000 00000001
    Number of active channels: 2
    19 Config 0: 08 7F 00001000 01111111
    1A Config 1: 08 60 00001000 01100000

    1B Config 2: 08 60 00001000 01100000
    1C Config 3: 08 60 00001000 01100000
    1D Config 4: 08 60 00001000 01100000
    1E Config 5: 08 60 00001000 01100000
    1F Config 6: 08 60 00001000 01100000
    20 Config 7: 08 60 00001000 01100000
    21 Filter 0: 06 00 78 00000110 00000000 01111000
    22 Filter 1: 06 01 80 00000110 00000001 10000000
    23 Filter 2: 06 01 80 00000110 00000001 10000000
    24 Filter 3: 06 01 80 00000110 00000001 10000000
    25 Filter 4: 06 01 80 00000110 00000001 10000000
    26 Filter 5: 06 01 80 00000110 00000001 10000000
    27 Filter 6: 06 01 80 00000110 00000001 10000000
    28 Filter 7: 06 01 80 00000110 00000001 10000000
    Write ADC Control: 06 00 00000110 00000000
    Read ADC Control: 06 00 00000110 00000000
    Timeout: 1129
    Data: 77fe99 Status: 00 Error: 00 00 00 00000000 00000000 00000000
    Timeout: 1118
    Data: 88003c Status: 01 Error: 00 00 00 00000000 00000000 00000000
    Timeout: 1121
    Data: 77fe8c Status: 00 Error: 00 00 00 00000000 00000000 00000000
    Timeout: 1123
    Data: 880052 Status: 01 Error: 00 00 00 00000000 00000000 00000000

  • With everything disconnected from the EVAL board except the supplied wall wart, I measured approximately 9 VDC on C46 and 1.9 VDC on C43 and 1.9 on AVDD J10/J11. U7 is marked with an "L2Z".  U4 is marked with an "L2M". When running the EVAL board from the wall wart, is it a singled ended supply and shouldn't AVdd be 3.3 VDC?  This would explain why the digital side is working fine but the analog side is weird.

  • 0
    •  Analog Employees 
    on Nov 6, 2017 12:34 AM

    Hi,

    Yes, the AVDD should be 3.3V. The analog part will not power up if AVDD is below the minimum specified level of 2.7V(low and mid power mode) and 2.9V (full power mode). Can you check if all of the jumpers and connections are at all default connections as shown on the user guide? AVDD is 3.3V at default settings. If everything is at default setup, try to remove any link at SL7 and check again the output of ADP1720 (U7). This is just to check if the regulator is providing the correct output voltage of 3.3V. Try also to check if there are any other shorted connections on the board that should not be connected.

    Thanks,

    Jellenie 

  • 0
    •  Analog Employees 
    on Aug 2, 2018 3:58 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin